1. Logic Gate Delay Modeling -1 Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore bpdas@cedt.iisc.ernet.in

2. OUTLINE Motivation Delay Model History Delay Definition Types of Models -RC delay Models -Logical Effort Limitation of Logical Effort Summary

3. Motivation Why Model is required? –For fast simulation –Solving differential equation is difficult –For creating optimal design –Real design will be always more costly and time consuming.So model is used to simulate the system before actual implementation.

4. Types of Models Physical Models –Based on Physical phenomena of device Empirical Models –Based on curve fitting ( i.e. Quadratic,Cubic etc.) –No physical significance. Table Models –Storing the data in a Lookup Table –Do interpolation between stored data

5. Delay Model History Courtesy : Synopsys

6. Delay Definitions t pdr : rising propagation delay –From input to rising output crossing V DD /2 t pdf : falling propagation delay –From input to falling output crossing V DD /2 t pd : average propagation delay –t pd = (t pdr + t pdf )/2 t r : rise slew –From output crossing 0.2 V DD to 0.8 V DD t f : fall slew –From output crossing 0.8 V DD to 0.2 V DD

7. t cdr : rising contamination delay –From input to rising output crossing V DD /2 t cdf : falling contamination delay –From input to falling output crossing V DD /2 t cd : average contamination delay –t pd = (t cdr + t cdf )/2 Delay Definitions

8. t pdr : rising propagation delay –From input to rising output crossing V DD /2 t pdf : falling propagation delay –From input to falling output crossing V DD /2 t pd : average propagation delay –t pd = (t pdr + t pdf )/2 t r : rise time –From output crossing 0.2 V DD to 0.8 V DD t f : fall time –From output crossing 0.8 V DD to 0.2 V DD Delay Definitions

9. t cdr : rising contamination delay –From input to rising output crossing V DD /2 t cdf : falling contamination delay –From input to falling output crossing V DD /2 t cd : average contamination delay –t pd = (t cdr + t cdf )/2 Delay Definitions

10. RC Delay Models Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

11. Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

12. Example: 3-input NAND

13. Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

14. 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

15. 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

16. 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

17. Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

18. Example: 2-input NAND Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

19. Example: 2-input NAND Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

20. Example: 2-input NAND Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

21. Example: 2-input NAND Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

22. Example: 2-input NAND Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

23. Example: 2-input NAND Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

24. Delay Components Delay has two parts –Parasitic delay 6 or 7 RC Independent of load –Effort delay 4h RC Proportional to load capacitance

25. Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously

26. Layout Comparison Which layout is better?

27. Delay in a Logic Gate Express delays in process-independent unit Delay has two components f is due to external loading p is due to self loading τ = 3RC = FO1 delay without parasitic delay

28. Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = gh (a.k.a. stage effort) –Again has two components τ = 3RC = FO1 delay without parasitic delay

29. Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = gh (a.k.a. stage effort) –Again has two components g: logical effort –Measures relative ability of gate to deliver current –g 1 for inverter τ = 3RC = FO1 delay without parasitic delay

30. Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = gh (a.k.a. stage effort) –Again has two components h: electrical effort = C out / C in –Ratio of output to input capacitance –Sometimes called fanout τ = 3RC = FO1 delay without parasitic delay

31. Delay in a Logic Gate Express delays in process-independent unit Delay has two components Parasitic delay p –Represents delay of gate driving no load –Set by internal parasitic capacitance τ = 3RC = FO1 delay without parasitic delay

32. Effort Delay Logical Effort g = C ingate /C in_unit_inv Electrical Effort h= C out / C ingate f = g*h = (C ingate /C in_unit_inv )*(C out / C ingate ) = (C out / C in_unit_inv ) (D actual ) ext = g*h * τ = (C out / C in_unit_inv )*3*R*C = (C out / C in_unit_inv )*R*C in_unit_inv = C out *R

33. Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widths

34. Catalog of Gates Gate typeNumber of inputs 1234n Inverter1 NAND4/35/36/3(n+2)/3 NOR5/37/39/3(2n+1)/3 Tristate / mux22222 XOR, XNOR4, 46, 12, 68, 16, 16, 8 Logical effort of common gates

35. Catalog of Gates Gate typeNumber of inputs 1234n Inverter1 NAND234n NOR234n Tristate / mux24682n XOR, XNOR468 Parasitic delay of common gates –In multiples of p inv ( 1)

36. Delay Plots d = f + p = gh + p

37. Delay Plots d = f + p = gh + p What about NOR2?

38. Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay:d = Frequency:f osc =

39. Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay:d = 2 Frequency:f osc = 1/(2*N*d) = 1/4N

40. Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = Electrical Effort:h = Parasitic Delay: p = Stage Delay:d =

41. Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay:d = 5 The FO4 delay is about 200 ps in 0.6 m process 60 ps in a 180 nm process f/3 ns in an f m process

42. Multistage Logic Networks

43. Limits of Logical Effort Chicken and egg problem –Need path to compute G –But dont know number of stages without G Simplistic delay model –Neglects input rise time effects Interconnect –Iteration required in designs with wire Maximum speed only –Not minimum area/power for constrained delay

44. Summary RC Delay Model Delay measurement using Logical Effort Method Gate sizing using Logical Effort for minimum delay Limitations of Logical Effort

45. Reference N. H. E. Weste and D. Harris, CMOS VLSI Design, A circuits and Systems Perspective 3 rd edition Pearson Addison Wesley Rabaey, Chandrakasan and Nikolic, Digital Integrated Circuits, a Design Perspective, Pearson Education