2. Other Gate Types Why? Gate classifications
Low cost implementation
Useful in implementing Boolean functions
Convenient conceptual representation
Gate classifications
Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus optional inversion(s).
Complex gate - a gate that requires more than one primitive operation type for its description
Primitive gates will be covered first

3. NAND Gate
The basic NAND gate has the following symbol and truth table:
AND-Invert (NAND) Symbol:
NAND represents NOT AND. The small “bubble” circle represents the invert function
The NAND gate is implemented efficiently in CMOS technology in terms of chip area and speed X Y
NAND 1 X Y
X · Y

4. NAND Gate: Invert-OR Symbol
Applying DeMorgan's Law: Invert-OR = NAND
This NAND symbol is called Invert-OR
Since inputs are inverted and then ORed together
AND-Invert & Invert-OR both represent NAND gate
Having both makes visualization of circuit function easier
Unlike AND, the NAND operation is NOT associative
(X NAND Y) NAND Z ≠ X NAND (Y NAND Z) X Y
X + Y = X · Y = NAND

5. The NAND Gate is Universal
NAND gates can implement any Boolean function
NAND gates can be used as inverters, or to implement AND / OR operations
A NAND gate with one input is an inverter
AND is equivalent to NAND with inverted output
OR is equivalent to NAND with inverted inputs X Y
X · Y ≡
X · Y= X+Y X Y
X + Y ≡

6. NOR Gate The basic NOR gate has the following symbol and truth table:
OR-Invert (NOR) Symbol:
NOR represents NOT OR. The small “bubble” circle represents the invert function.
The NOR gate is also implemented efficiently in CMOS technology in terms of chip area and speed X Y
NOR 1 X Y
X + Y

7. NOR Gate: Invert-AND Symbol
The Invert-AND symbol is also used for NOR
This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together
OR-Invert & Invert-AND both represent NOR gate
Having both makes visualization of circuit function easier
Unlike OR, the NOR operation is NOT associative
(X NOR Y) NOR Z ≠ X NOR (Y NOR Z) X Y
X · Y = X + Y = NOR

8. The NOR Gate is also Universal
NOR gates can implement any Boolean function
NOR gates can be used as inverters, or to implement AND / OR operations
A NOR gate with one input is an inverter
OR is equivalent to NOR with inverted output
AND is equivalent to NOR with inverted inputs X Y
X + Y ≡ X Y
X + Y= X · Y
X · Y ≡

9. NAND–NAND Implementation
Consider the Following SOP Expression:
A 2-level AND-OR circuit can be converted easily to a NAND-NAND implementation X Z W Y F X Z W Y F
Two successive bubbles on the same line cancel each other X Z W Y F

10. NOR–NOR Implementation
Consider the Following POS Expression:
A 2-level OR-AND circuit can be converted easily to a NOR-NOR implementation X Z W Y F X Z W Y F
Two successive bubbles on the same line cancel each other X Z W Y F

11. Other Types of 2-Level Circuits
Other useful types of 2-level circuits:
AND-NOR and NAND-AND
OR-NAND and NOR-OR
AND-NOR Function:
Similarly, OR-NAND circuits can be converted to NOR-OR X Y W Z F
AND-NOR X Y W Z F
NAND-AND X Y W Z F

12. Exclusive OR / Exclusive NOR
The eXclusive-OR (XOR) function is an important Boolean function used extensively in logic circuits
The XOR function may be:
Implemented directly as an electronic circuit (true gate)
Implemented by interconnecting other gate types (XOR is used as a convenient representation)
The eXclusive-NOR (XNOR) function is the complement of the XOR function
XOR and XNOR gates are complex gates

13. XOR / XNOR Tables and Symbols
X  Y 1 X Y
X  Y 1
XOR Symbol
XNOR Symbol
Because it is defined as X Y + X’ Y’ that equals 1 if and only if X = Y implying X is equivalent to Y.
The XNOR is also denoted as equivalence

14. Uses for XOR / XNOR SOP Expressions for XOR/XNOR:
The XOR function is:
The eXclusive NOR (XNOR) function, know also as equivalence is:
Uses for the XOR and XNORs gate include:
Adders/subtractors/multipliers
Counters/incrementers/decrementers
Parity generators/checkers
Strictly speaking, XOR and XNOR gates do no exist for more that two inputs. Instead, they are replaced by odd and even functions. Y X + = Å Y X + = Å

15. XOR Implementations SOP implementation for XOR: X  Y = X Y + X Y
NAND only
implementation
for XOR: X Y X Y

16. XOR / XNOR Identities XOR and XNOR are associative operations X = Å 1Å = X 1 Å X = Å 1 X = Å X Y Å =
Y = X  Y X Y Å =
) = X  Y  Z Z Y ( X ) Å =
) = X  Y  Z Z Y ( X ) Å =
XOR and XNOR are associative operations

17. Odd Function + = Å Z Y X X  Y  Z W  X  Y  Z
The XOR function can be extended to 3 or more variables
For 3 or more variables, XOR is called an odd function
The function is 1 if the total number of 1’s in the inputs is odd + = Å Z Y X 1 YZ X 00 01 11 10 WX
X  Y  Z
W  X  Y  Z

18. Odd and Even Functions
The 1s of an odd function correspond to inputs with an odd number of 1s
The complement of an odd function is called an even function
The 1s of an even function correspond to inputs with an even number of 1s
Implementation of odd and even functions use trees made up of 2-input XOR or XNOR gates

19. Odd/Even Function Implementation
Design a 3-input odd function with 2-input XOR:
3-input odd function:
F = (X  Y)  Z
Design a 4-input even function with 2-input XOR and XNOR gates:
4-input even function:
F = (W  X)  (Y  Z) X Y Z F W X Y F Z

20. Parity Generators and Checkers
A parity bit added to n-bit code produces (n+1)-bit code with an odd (or even) count of 1s
Odd Parity bit: count of 1s in (n+1)-bit code is odd
So use an even function to generate the odd parity bit
Even Parity bit: count of 1s in (n+1)-bit code is even
So use an odd function to generate the even parity bit
To check for odd parity
Use an even function to check the (n+1)-bit code
To check for even parity
Use an odd function to check the (n+1)-bit code

21. Parity Generator & Checkers
Sender
Receiver
n-bit code
Parity
Generator
(n+1)-bit code
Checker
Error
Design an even parity generator and checker for 3-bit codes
Solution: Use 3-bit odd function
to generate even parity bit
Use 4-bit odd function to check
for errors in even parity codes
Operation: (X,Y,Z) = (0,0,1) gives
(X,Y,Z,P) = (0,0,1,1) and E = 0
If Y changes from 0 to 1 between
generator and checker, then E = 1 indicates an error X Y Z P X Y Z E P

22. Buffer A buffer is a gate with the function F = X
In terms of Boolean function,
a buffer is the same as a connection!
So why use it?
A buffer is used to amplify an input signal
Permits more gates to be attached to output
Also, increases the speed of circuit operation X F 1 X F

23. Hi-Impedance Output Logic gates introduced thus far …
Have 1 and 0 output values
Cannot have their outputs connected together
Three-state logic adds a third logic value:
Hi-Impedance output: Hi-Z
What is Hi-Impedance output?
The output appears to be disconnected from the input
Behaves as an open circuit between gate input & output
Hi-Z state makes a gate output behave differently:
Three output values: 1, 0, and Hi-Z
Hi-impedance gates can connect their outputs together

24. The 3-State Buffer Symbol Truth Table IN = data input
EN = Enable control input
OUT = data output
If EN = 0 then OUT = HI-Z
Regardless of the value on IN
Output disconnected from input
If EN = 1, then OUT =IN
Output follows the input value
Variations:
EN can be inverted
OUT can be inverted
By addition of bubbles to signals
Symbol IN EN
OUT
Truth Table EN IN
OUT X
Hi-Z 1

25. Wired Output: Resolving Output Value
The output of 3-state buffers can be wired together
At most one 3-state buffer can be enabled. Resolved output is equal to the output of the enabled 3-state buffer
If multiple 3-state buffers are enabled at the same time then conflicting outputs will burn the circuit
IN0
EN0
OUT
IN1
EN1
IN2
EN2 O0 O1 O2
Resolution Table O0 O1 O2
OUT
0 or 1
Hi-Z
Burn

26. Data Selection Circuit
Performing data selection with 3-state buffers:
If S = 0 then OUT = IN0 else OUT = IN1
The outputs of the 3-state buffers are wired together
Since EN0 = S and EN1 = S, one of the two buffer outputs is always Hi-Z
IN0
EN0 S
OUT
IN1
EN1 S
EN0
EN1
IN0
IN1
OUT 1 X

27. Implementing a XOR Gate
We can use 3-state buffers to implement a XOR gate as shown
B = 0 will enable the 3-state buffer with output X (F = X = A)
B = 1 will enable the 3-state buffer with output Y (F = Y = A)
Therefore, F = A  B A
F = AB B X Y
Truth Table A B X Y F
Hi-Z 1

28. Terms of Use
All (or portions) of this material © 2008 by Pearson Education, Inc.
Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and Computer Design Fundamentals as the course textbook.
These materials or adaptations thereof are not to be sold or otherwise offered for consideration.
This Terms of Use slide or page is to be included within the original materials or any adaptations thereof.