1. Lecture 4 Combinational Logic Implementation Technologies
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
ECE C03 Lecture 4

2. Outline Review of Combinational Logic Technologies
Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, , 5.7, 6.2
ECE C03 Lecture 4

3. Programmable Arrays of Logic Gates
Until now, we learned about designing Boolean functions using discrete logic gates
We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure
Specific functions can be programmed
Can use programmable logic arrays (PLA) or programmable array logic (PAL)
ECE C03 Lecture 4

4. PALs and PLAs
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form
ECE C03 Lecture 4

5. Why PALs/PLAs Work Equations F0 = A + B' C' F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Key to Success: Shared Product Terms
Example:
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Personality Matrix
Output Side:
1 = term connected to output
0 = no connection to output
ECE C03 Lecture 4

6. Example of PALs and PLAs
All possible connections are available
before programming
ECE C03 Lecture 4

7. Example of PALs and PLAs (Contd)
Unwanted connections are "blown"
Note: some array structures
work by making connections
rather than breaking them
ECE C03 Lecture 4

8. Alternative Representations
Short-hand notation
so we don't have to
draw all the wires!
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
ECE C03 Lecture 4

9. Design Example Multiple functions of A, B, C F1 = A B C F2 = A + B + C
F5 = A xor B xor C
F6 = A xnor B xnor C B C A B C
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ECE C03 Lecture 4 F1 F2 F3 F4 F5 F6

10. Differences Between PALs and PLAs
PAL concept — implemented by Monolithic Memories
constrained topology of the OR Array
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept — generalized topologies in AND and OR planes
ECE C03 Lecture 4

11. Design Example: BCD-to-Gray Code Converter
Truth Table
K-maps AB CD 00 01 11 10 D B C A X 1
K-map for W AB CD 00 01 11 10 D B C A 1 X
K-map for AB CD 00 01 11 10 D B C A 1 X
K-map for Y AB CD 00 01 11 10 D B C A X 1
K-map for Z
Minimized Functions:
W = A + B D + B C
X = B C'
Y = B + C
Z = A'B'C'D + B C D + A D' + B' C D'
ECE C03 Lecture 4

12. Programmed PAL 4 product terms per each OR gate ECE C03 Lecture 4
A B C D
ECE C03 Lecture 4
4 product terms per each OR gate

13. Generalized Building Blocks
Non-Gate Logic
So far we have seen:
AND-OR-Invert
PAL/PLA
Generalized Building Blocks
Beyond Simple Gates
Kinds of "Non-gate logic":
• switching circuits built from CMOS transmission gates
• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories
ECE C03 Lecture 4

14. Steering Logic: Switches
Voltage Controlled Switches
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is formed
ECE C03 Lecture 4

15. Switching or Steering Logic
Voltage Controlled Switches
Logic 1 on gate,
Source and Drain connected
Logic 0 on gate,
Source and Drain connected
ECE C03 Lecture 4

16. Logic Gates with Steering Logic
Logic Gates from Switches
+5V A B A B
+5V
+5V
A B A A
A + B
Inverter
NAND Gate
NOR Gate
Pull-up network constructed from pMOS transistors
Pull-down network constructed from nMOS transistors
ECE C03 Lecture 4

17. Inverter with Steering Logic
Inverter Operation
+5V
+5V
"1"
"0"
"0"
"1"
Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND
Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD
ECE C03 Lecture 4

18. NAND Gate with Steering Logic
NAND Gate Operation
"1"
"1"
"0"
"1"
+5V
+5V
"0"
"1"
A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND
A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD
ECE C03 Lecture 4

19. NOR Gate with Steering Logic
NOR Gate Operation
"0"
"0"
"1"
"0"
+5V
+5V
"1"
"0"
A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD
A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND
ECE C03 Lecture 4

20. CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Control
Control
Control In
Out In
Out In
Out
Control
Control
Control
Switches
Transistors
Transmission or
"Butterfly" Gate
ECE C03 Lecture 4

21. Selection/Demultiplexing1 Z
Selector:
Choose I0 if S = 0
Choose I1 if S = 1 S S Z
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1 S I S Z 1 S
ECE C03 Lecture 4

22. Use of Multiplexers or DemultiplexersA Y
Demultiplexers
Multiplexers B Z A Y
Demultiplexers
Multiplexers B Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination
interconnect
ECE C03 Lecture 4

23. Well-formed Switching Logic
Problem with the Demux implementation:
multiple outputs, but only one connected to the input! S Z S
"0" I S S Z 1 S
"0" S
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"
ECE C03 Lecture 4

24. Use of Multiplexers/Selectors
Multi-point connections A0 A1 B0 B1
Multiple input sources Sa
MUX
MUX Sb A B
Sum Ss
DEMUX
Multiple output destinations S0 S1
ECE C03 Lecture 4

25. General Concept of Using Multiplexers
2 data inputs, n control inputs, 1 output
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output n
Z = A' I A I 1 A 1 Z I 1 I 1 I 1 A 1 Z 1
Functional form
Logical form
Two alternative forms
for a 2:1 Mux Truth Table
ECE C03 Lecture 4

26. Use of Multiplexers/Selectors
2:1
mux
Z = A' I A I Z 1 I 1 A I I 1
4:1
mux Z
Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 I 2 I 3 A B I I 1 I 2 I 3
8:1
mux
Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 I 4 Z I 5 I 6 n I 7
2 -1
In general, Z = S m I
k=0 k k n
in minterm shorthand form for a 2 :1 Mux A B C
ECE C03 Lecture 4

27. Alternative ImplementationB I0 Z I1 I2 I3
Gate Level
Implementation
of 4:1 Mux
Transmission Gate
Implementation of
4:1 Mux
twenty transistors
thirty six transistors
ECE C03 Lecture 4

28. Design of Large Multiplexers
Large multiplexers can be implemented by cascaded smaller ones I 1 2 3
8:1
mux
Control signals B and C simultaneously
choose one of I0-I3 and I4-I7
Control signal A chooses which of the
upper or lower MUX's output to gate to Z
4:1
mux I 1 I 2 I 3 S 1
2:1
mux Z I 4 1 2 3 1
4:1
mux S I 5 I I 6 I 1 1 S I 7 S 1 C I B C A 2 I 3 1 S 1
Alternative 8:1 Mux Implementation C Z 2 I 4 3 S0 S1 I 5 1 S A B C I 6 I
ECE C03 Lecture 4 7 1 S C

29. Multiplexers/Selectors as General Purpose Blocks
:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1) A B C F 1 1 1 C C 1 F 2 1 C 1
4:1 F
8:1 3 1 1 2
MUX 4
MUX C 1 1 1 3 5
S1 S0 1 1 6 A B 1 7
S2 S1 S0 1 1 1 1 1 1 A B C 1 1 1 1
"Lookup Table"
ECE C03 Lecture 4

30. Generalization of Multiplexer/Selector Logic… I 1 I 2 I n F 1 I n 1 I n 1
Four possible
configurations
of the truth table rows …
n-1 Mux
control variables 1
single Mux
data variable
Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX: 1 D 1 2 3 4 5 6 7
K-map
Choose A,B,C
as control variables G
8:1
mux
Multiplexer
Implementation S 2 1
TTL package efficient
May be gate inefficient A B C
ECE C03 Lecture 4

31. Decoders/Demultiplexersn
Decoder: single data input, n control inputs, 2 outputs
control inputs (called select S) represent Binary index of output to which
the input is connected
data input usually called "enable" (G)
1:2 Decoder:
3:8 Decoder:
O0 = G • S; O1 = G • S
O0 = G • S0 • S1 • S2
O1 = G • S0 • S1 • S2
O2 = G • S0 • S1 • S2
O3 = G • S0 • S1 • S2
O4 = G • S0 • S1 • S2
O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
O7 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1
O1 = G • S0 • S1
O2 = G • S0 • S1
O3 = G • S0 • S1
ECE C03 Lecture 4

32. Alternative ImplementationsG /G
Output0
Output0
Select
Select
Output1
Output1
1:2 Decoder, Active High Enable
1:2 Decoder, Active Low Enable /G G
Output0
Output0
Output1
Output1
Output2
Output2
Output3
Output3
Select0
Select1
Select0
Select1
2:4 Decoder, Active High Enable
2:4 Decoder, Active Low Enable
ECE C03 Lecture 4

33. Switch Level Implementations
Select
Select G
Output G
Output
Select
Select
Select
"0"
Select
Select
Output 1
Select
Select
Output 1
Select
Naive, Incorrect Implementation
All outputs not driven at all times
Select
"0"
Select
Correct 1:2 Decoder Implementation
ECE C03 Lecture 4

34. Switch Implementation of 2:4 DecoderG
Output
"0"
Select 1 2 3
Operation of 2:4 Decoder
S0 = 0, S1 = 0
one straight thru path
three diagonal paths
ECE C03 Lecture 4

35. Decoder as a Logic Building Block1 2 3 4 5 6 7
ABC
Decoder Generates Appropriate
Minterm based on Control Signals
Enb
3:8
dec S 2 1 A B C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
ECE C03 Lecture 4

36. Decoder as a Logic Building Block1 2 3 4 5 6 7 8 9 10 12 13 14 15 A
B C D F 1
Enb
4:16
dec F 2 F 3 S 3 2 1 A B C D
If active low enable, then use NAND gates!
ECE C03 Lecture 4

37. Read-Only Memories ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V
+5V
+5V
+5V n
2 -1 i
Word Line 0011
Dec j
Word Line 1010
Bit Lines
n-1
Address
ECE C03 Lecture 4
Internal Organization

38. Implementing Logic with ROMs
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
Address A 1 B 1 C 1 F 1 F 1 F 2 1 F 3 1 W
ord Contents
ROM
8 w
ords
4 bits by A B C F F 1 F 2 F 3
address
outputs
ECE C03 Lecture 4

39. ROMs vs PLAs Not unlike a PLA structure with a fully decoded
AND array!
Memory
array
Decoder 2 n
word
lines 2 n
words by m
bits n
address
lines m
output
lines
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
ECE C03 Lecture 4

40. Summary Review of Combinational Logic Technologies
Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, , 5.7, 6.2
ECE C03 Lecture 4