1. Digital CMOS Logic Circuits
CMOS digital circuits:
small size
ease of fabrication
low power dissipation
CMOS Inverter
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Figure (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

2. Dynamic Operation of CMOS Inverter
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Figure Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an identical inverter formed by Q3 and Q4.

3. sedr42021_1007a.jpg
Figure Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.

4. Basic Structure of CMOS Logic Gate Circuits
alternative circuit symbols
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Figure Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.

5. CMOS NOR Gate
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Figure A two-input CMOS NOR gate.

6. CMOS NAND Gate sedr42021_1013.jpg
Figure A two-input CMOS NAND gate.

7. sedr42021_1014.jpg
Figure CMOS realization of a complex gate.

8. CMOS XOR Gate sedr42021_1015a.jpg
Figure Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27).

9. Transistor Sizing sedr42021_1016.jpg
Figure Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.

10. sedr42021_1017.jpg
Figure Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.