1. High-Level Fault Grading

2. Improving Gate-Level Fault Coverage by RTL Fault Grading* * W. Mao and R. K. Gulati, ITC 1996, pp. 150-159.

3. High-Level Fault Grading3 Motivation Gate-level fault simulation is computationally infeasible for large circuits RTL design available early in the design cycle for fault grading of available (validation or legacy) test vectors It would be nice if fault analysis could be done at RTL level but the results closely approximated gate-level coverage.

4. High-Level Fault Grading4 Basic Idea Inject stuck-type faults on all PIs, internal signals, and their fanouts using RTL constructs. Use an RTL fault simulator (e.g. Verifault for Verilog) for fault grading at the RTL level Verify the closeness of approximation against gate-level fault coverage.

5. High-Level Fault Grading5 Example RTL Model and Signal- Flow Diagram

6. High-Level Fault Grading6 RTL Modified for Fault Injection

7. High-Level Fault Grading7 Testability Analysis Flow

8. High-Level Fault Grading8 Handling Signal Fanouts (Optimistic Mode)

9. High-Level Fault Grading9 Handling Signal Fanouts (Pessimistic Mode)

10. High-Level Fault Grading10 RTL vs. Gate-Level Fault Coverage

11. High-Level Fault Grading11 Critique Technique works well only when the circuit is simulated at low-level RTL Errors arise because of: Differences in fanouts at the two levels Most signal fanout lot more at the RTL level (exception: Reset signal) Complex blocks with only I/O visibility The last shortcoming is addressed in the stratified sampling approach of Thaker, Agrawal, and Zaghloul that we consider next.

12. Stratified Sampling for Fault Coverage of VLSI Systems Vishwani D. Agrawal Auburn University Collaborators: Pradip Thaker and Mona Zaghloul

13. High-Level Fault Grading13 VLSI System Design Register-transfer level (RTL) design and verification Logic synthesis Test generation Design and test data for manufacturing 90-100% stuck-at fault coverage required Timing and physical design

14. High-Level Fault Grading14 Problem Accurately estimate the gate-level fault coverage for a VLSI system at the RT-level Advantages: Improve test Improve design Avoid expensive design changes Previous approaches do not accurately represent gate-level fault coverage (function errors, mutation, statement faults, branch faults, etc.)

15. High-Level Fault Grading15 Solution Model faults as representative sample of the targeted (gate-level stuck-at) faults. Treat the coverage in an RTL module as a statistical sampling estimate. For a multi-module VLSI system, combine module coverages according to the stratified sampling technique.

16. High-Level Fault Grading16 Outline of Talk Introduction to fault sampling. RTL fault model and application to modules. Coverage in a multi-module system: Need for stratified sampling Stratum weights Experimental results Conclusion References

17. High-Level Fault Grading17 Fault Sampling A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults.

18. High-Level Fault Grading18 Random Sampling Model All faults with a fixed but unknown coverage Detected fault Undetected fault Random picking N p = total number of faults (population size) C = fault coverage (unknown) N s = sample size N s << N p c = sample coverage (a random variable)

19. High-Level Fault Grading19 Probability Density of Sample Coverage, c (x--C ) 2 -- ------------ 1 2 2 p (x ) = Prob(x < c < x +dx ) = -------------- e 2 1/2 p (x ) C C +3 C -3 1.0 x Sample coverage C (1 - C) Variance 2 = ------------ N s Mean = C Sampling error x

20. High-Level Fault Grading20 Sampling Error Bounds C (1 - C ) | x - C | = 3 -------------- 1/2 N s Solving the quadratic equation for C, we get the 3-sigma (99.8% confidence) estimate (Agrawal-Kato, 1990): 4.5 C 3 = x ------- [1 + 0.44 N s x (1 - x )] 1/2 N s Where N s is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults. Millot, 1923

21. High-Level Fault Grading21 An RTL Fault Model (ITC-2000) Language operators are assumed to be fault-free Variables (map onto signal lines) contain faults stuck-at-0 stuck-at-1 Only one fault is applied at a time (single fault assumption)

22. High-Level Fault Grading22 RTL Fault Injection Not affected by faults: Synthetic operators + - * >= <= == != Boolean operators & | ^ ~ Logical operators && || ! Sequential elements (flip-flops & latches) Faults introduced in signal variables (stems and fan-outs) Separate faults for bits of data words

23. High-Level Fault Grading23 Fault Modeling for Boolean Operators

24. High-Level Fault Grading24 Stem and Fan-out Fault Modeling RTL fan-out faults: if(X) then Z=Y; else Z=!Y; Unique RTL fault is placed on each fan-out of each bit of a variable Unique RTL fault on each stem

25. High-Level Fault Grading25 More RTL Faults

26. High-Level Fault Grading26 Observations and Assumption: RTL Faults RTL faults may have detection probability distribution similar to that of collapsed gate-level faults Statistically, an RTL fault-list approximates a random sample from the gate-level fault-list Number of RTL faults vs. gate-level faults depends on Level of RTL description Synthesis procedure used to convert RTL to gate level

27. High-Level Fault Grading27 RTL Fault Simulation Analogous to gate-level approach Faults injected in RTL code of the design description by a C++ parser; a logic buffer element inserted at fault site (technique identical to Mao & Gulatis). Fault report contains statistics on detected and undetected RTL faults Cadences Verifault-XL used as RTL fault simulator

28. High-Level Fault Grading28 Estimation Error for Module Fault Coverage RTL fault coverage assumed to be an estimate of the collapsed gate-fault coverage within statistical bound [Agrawal and Kato, D&T, 1990] : a = 3.00 for confidence probability of 99.8% c = ratio of detected to total number of RTL faults M = number of gate faults N = number of RTL faults, k = 1 - N/M

29. High-Level Fault Grading29 DSP Interface Module (3,168 Gates)

30. High-Level Fault Grading30 RTL Faults and VLSI System Coverage Experimental results demonstrate RTL fault coverage of a module to be a good statistical estimate of the gate-level fault coverage A VLSI system consists of many interconnected modules Overall RTL fault-list of a VLSI system does not constitute a representative sample of the gate-level fault-list

31. High-Level Fault Grading31 Error at System Level RTL Coverage = (0.91 x 100 + 0.39 x 100) / 200 = 65% Gate Coverage = (0.90 x 150 + 0.40 x 400) / 550 = 54% A correct estimation of gate-level fault coverage from RTL coverage: 91 x (150 / 550) + 39 x (400 / 550) = 53% M2 100 faults 39% cov. M1 100 faults 91% cov. M1 150 faults 90% cov. M2 400 faults 40% cov. RTL Gate- level

32. High-Level Fault Grading32 Application of Stratified Sampling Fault population of a VLSI system divided into strata according to RTL module boundaries RTL faults in each module are considered a sample of corresponding gate-level faults The stratified RTL coverage is an estimate of the gate-level coverage: W m = stratum weight of m th module = G m /G c m = RTL fault coverage of m th module G m = number of gate-level faults in m th module G = number of all gate-level faults in the system M = number of RTL modules in the system M C = W m c m m=1

33. High-Level Fault Grading33 Application of Stratified Sampling Range of coverage, where, r m = number of RTL faults in m th module t = value from tables of normal distribution The technique requires knowledge of stratum weights and not absolute values of G m and G c m (1 c m ) WmWm r m 1 m=1 M C + t

34. High-Level Fault Grading34 Stratum Weight Extraction Techniques Logic synthesis based weight extraction W m = G m /G Floor-planning based weight extraction W m = A m /A Entropy-measure based weight extraction

35. High-Level Fault Grading35 Experimental Procedure Technology-dependent weight extraction Several unique gate-level netlists obtained by logic synthesis from the same RTL code Each synthesis run performed using a different set of constraints, e.g., area optimization (netlist 1), speed optimization (netlist 2), or combined area and speed optimizations (netlists 3 and 4) Strata weights calculated using gate-level fault lists of various synthesized netlists Technology-independent weight extraction Stratum weights calculated using area distribution among modules Each set of stratum weights used to calculate RTL fault coverage and error bounds Impact of estimation error investigated

36. High-Level Fault Grading36 Experimental Data: Weight Distributions

37. High-Level Fault Grading37 Experimental Data: RTL Fault Coverage

38. High-Level Fault Grading38 Experimental Data: Error Bounds

39. High-Level Fault Grading39 Timing Controller ASIC (17,126 Gates)

40. High-Level Fault Grading40 A DSP ASIC (104,881 Gates)

41. High-Level Fault Grading41 Conclusion Main ideas of RTL fault modeling A small or high-level RTL module contributes few RTL faults, but large statistical tolerance gives a correct coverage estimate Stratified sampling accounts for varying module sizes and for different RTL details that may be used Stratum weights appear to be insensitive to specific details of synthesis Advantages of the proposed RTL fault model High-level test generation and evaluation Early identification of hard-to-test RTL architectures Potential for significantly reducing run-time penalty of the gate-level fault simulation

42. High-Level Fault Grading42 References - 1 V. D. Agrawal, Sampling Techniques for Determining Fault Coverage in LSI Circuits, J. Digital Systems, vol. V, no. 3, pp. 189-202, 1981. V. D. Agrawal and H. Kato, Fault Sampling Revisited, IEEE Design & Test of Computers, vol. 7, no. 4, pp. 32-35, Aug. 1990. P. A. Thaker, M. E. Zaghloul, and M. B. Amin, Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementation, Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 256-259. P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test, Proc. 17th IEEE VLSI Test Symp., Apr. 1999, pp. 182-188.

43. High-Level Fault Grading43 References - 2 P. A. Thaker, Register-Transfer Level Fault Modeling and Evaluation Techniques, PhD Thesis, George Washington University, Washington, D.C., May 2000. P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, Register-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits, Proc. Int. Test Conf., Oct. 2000, pp. 940-949. This presentation is available from the website http://cm.bell-labs.com/cm/cs/who/va

44. High-Level Fault Grading44 Other Related Papers 1. OCCOM: Fallah et al., IEEE TCAD, Aug. 2001, pp. 1003-1015. 2. IFMB: Santos et al., ITC2001, pp. 377- 385. 3. Probabilistic Testability: Fernandes et al., DATE04, pp. 10176-10181. 4. Kang et al., VTS07.