1. IDEW06 Barcelona, September 5, 2006 1 Modeling and design of on-chip inter-block decoupling capacitors for PSN and EMI reduction Josep Rius 1 and Maurice Meijer 2 UPC 2 Digital Design and Test Group Philips Research Laboratories, The Netherlands 1 Departament dEnginyeria Electrònica Universitat Politècnica de Catalunya, Spain

2. IDEW06 Barcelona, September 5, 2006 2 Motivation Feature size[nm] gate switching time [ps] … 45 70 100 130 …. 10 This work concerns a model and design procedure for on-chip MOS decaps targeting PSN and EMI reduction high frequency content of PSN Small gate switching times Chip Package PCB Power supply ~mm ~ cm ~ 10cm Dimensions comparable to the wavelength of the HF components EMI On-chip decoupling capacitors (decaps) Effective solution to reduce power supply noise (PSN) Decreases current loops thereby reducing EMI Design constraints: performance, leakage, …

3. IDEW06 Barcelona, September 5, 2006 3 Proposed Decap Model Model characteristics: Distributed RGC model to take into account HF effects Gate leakage modeled by a voltage-dependent current source (B) rGrG GND V DD c rBrB n+ cBcB p+ GND substrate l i(v) r r G = poly gate resistance r = channel resistance c = gate to channel capacitance c B = channel to substrate capacitance r B = substrate resistance i(v) = direct tunneling gate current ALL PARAMETERS ARE PER UNIT LENGTH NMOS decap:

4. IDEW06 Barcelona, September 5, 2006 4 Proposed Decap Model (cntd) Model simplification: Exploit symmetry of the decap Poly gate resistance (r G ) << channel resistance (r) Channel-to-substrate capacitance (C B ) neglected r G = poly gate resistance r = channel resistance c = gate to channel capacitance c B = channel to substrate capacitance r B = substrate resistance i(v) = direct tunneling gate current ALL PARAMETERS ARE PER UNIT LENGTH NMOS decap:

5. IDEW06 Barcelona, September 5, 2006 5 MOS Decaps: Analytical Solution Diffusion equation with proper boundary and initial conditions V DD GND x 0 l r, c v(x,t) -l-l i(v) Gate leakage term Channel term Steady-state response can be separated into DC+AC solution

6. IDEW06 Barcelona, September 5, 2006 6 Example DC response. l = 10 m, w = 3 m, w = 3 m, 65nm CMOS Drop voltage along the channel increases with channel length Drop voltage along the channel increases as t OX is reduced Normalized distance along a half of channel length 90nm CMOS 65nm CMOS 45nm CMOS l = 5 m l = 10 m l = 20 m Normalized voltage along the channel +l+l 0 +l+l 0

7. IDEW06 Barcelona, September 5, 2006 7 Example AC response. No leakage case V M e j t r, c x +l+l 0 -l-l v(x,t) 1.1 1 0.9 0.8 0 L Normalized voltage along the channel Amplitude A(x) changes along the channel. It depends on r and c as well as 0 L Normalized voltage along the channel Normalized voltage along the channel 0 l maximum effective decap length

8. IDEW06 Barcelona, September 5, 2006 8 Example AC response. Leakage case V M e j t r, c x +l+l 0 -l-l v(x,t) g 1.1 1 0.9 0.8 0 L Normalized voltage along the channel Now L can be approximated by Normalized voltage along the channel 0 L Normalized voltage along the channel L 0 l Amplitude A(x) changes along the channel. It depends on r, c and g as well as

9. IDEW06 Barcelona, September 5, 2006 9 Input Impedance of a MOS Decap Z IN r, c g l Critical frequency at l= The frequency that separates lumped and distributed behaviour Lower critical frequency in case of gate oxide leakage NO LEAKAGE: LEAKAGE:

10. IDEW06 Barcelona, September 5, 2006 10 Normalized R and C as a function of frequency

11. IDEW06 Barcelona, September 5, 2006 11 Intra-block and Inter-block MOS decaps Digital logic block System-on-Chip Intra-block decaps have constrained dimensions – For example, the are implemented in the standard-cell template Inter-block decaps do not suffer from this constraint – Typically, used for EMI reduction purposes

12. IDEW06 Barcelona, September 5, 2006 12 WSWS (B) Y YVDD LFLF (A) ZZ GND VDD LFLF LFLF LFLF LFLF LFLF LFLF ZZZZZZZ GND VDD Example Inter-Block Decap: Gate length must be limited

13. IDEW06 Barcelona, September 5, 2006 13 Stripe VDD GND VDD GND VDD Stripe Finger Example Inter-Block Decap: Fingers and Stripes

14. IDEW06 Barcelona, September 5, 2006 14 Inter-Block Decap Model Parameters Channel sheet resistance [ /] Gate capacitance per unit area [F/m 2 ] Gate oxide conductance per unit area [S/m 2 ] Gate current density per unit area [A/m 2 ] Critical frequency Total gate-oxide leakage Total gate area [m 2 ] Model parameters are defined to be independent of length and width

15. IDEW06 Barcelona, September 5, 2006 15 Procedure for Optimum Inter-Block Decap Design 1. Define the total decoupling capacitance C DEC to be included in the IC 2. Determine the effective total area as 3. Obtain the gate length of a finger L F0 to get the maximum frequency f C for which the decap needs to perform 4. Define the number of gate fingers as 5. Obtain the gate length of a single decap as 6. Define the number of stripes as where W MAX is the maximum allowed gate width 7. Obtain the gate width of a single decap as 8. Calculate total leakage

16. IDEW06 Barcelona, September 5, 2006 16 Example 90nm GP technology Required decap C DEC = 1nF Three gate-oxide thicknesses red : tox = 6.5 nm magenta: tox = 5 nm black: tox = 1.6 nm Results: Area factor = 1.01 to 1.23 Total leakage current – I LEAK = 1.1 mA red : tox = 6.5 nm magenta: tox = 5 nm black: tox = 1.6 nm Total decap area vs. f C Gate length of a finger vs. f C

17. IDEW06 Barcelona, September 5, 2006 17 Conclusions Distributed decap model based on physical grounds Relevant parameters for each technology node are easily obtained Such parameters are independent of dimensions for inter-block decaps Critical Frequency f C qualifies decoupling performance Defines the border between full and reduced decap performance Relevant expressions have been derived Simple procedure to design inter-block decaps based on the proposed model