1. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 Large gate periphery InGaAs/InAlAs pHEMT: Measurement and Modelling for LNA fabrication B. Boudjelida, A. Sobih, A. Bouloukou, S. Boulay, J. Sexton, T. Tauqueer, J. Sly and M. Missous School of Electrical and Electronic Engineering University of Manchester

2. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 OUTLINE GOALS Low Fmin Low Rn ACTIVE DEVICES INTRINSIC PROPERTIES MODELLING RESULTS LNA SIMULATIONS QUICK ADC UPDATE CONCLUSIONS

3. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 Workflow at University of Manchester Material growthProcess set-up and fabrication DC & RF measurements Parameter extraction & device modelling Material assessment LNA circuit design LNA layout design (process integration) LNA Fabrication! Process set-up LNA building blocks library LNA testing

4. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 GOALS Low Fmin and Low Rn Four noise parameters F min : the minimum noise factor expected when Γ s = Γ opt, R n : the equivalent noise resistance, G opt and B opt : the real and imaginary parts of the optimal source admittance Y opt, for which For Broad band low noise amplification Need both low F min AND low Rn

5. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 GOALS Low Fmin and Low Rn Variation of Noise Resistance Rn with frequency and temperature. Variation of Fmin with frequency and temperature. Very difficult to achieve low Rn with submicron devices below 2GHz [*] M.R. Murti et al. IEE Transactions MTT 48(12), 2579, (2000). 300 K 200 K 18 K 300 K 200 K 18 K (NGST 0.1 x 80 um InGaAs-InAlAs Phemt [*])

6. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 ACTIVE DEVICES Increased gate metallisation thickness Gate thickness h (nm)R g (Ohm)NF min @ 2GHz (dB) 150211.2 5002.70.6 Comparison between VMBE#1841 transistors made with different gate metallisations (1x200μm devices, R g extracted, NF min calculated for k=3.6) The gate metallisation resistance key contributor to gate resistance For a fixed gate length: increasing gate thickness (h) reduces R g Why reduce it? Key parasitic contributor δ Ti/ Au AuGe/ Au h [1]: G. Vasilescu, Electronic noise and interfering signals, Springer-Verlag Berlin Heindelberg New York, 2005 [1]

7. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 ACTIVE DEVICES Latest results on R g and R n Normal trend for 2-finger devices shows an increase in R g with increasing gate size R g and R n extracted from linear and non-linear models, respectively. R n decreases with increasing gate size 2-finger topology Use of multi gate finger topology: Reduces R g to about 2 Ohms Makes R g insensitive to gate size Use of large multi gate finger devices is the key to: Maintaining a low R g Reducing R n The effect of topology on R g and R n XMBE#106 multi-finger topology

8. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 ACTIVE DEVICES Non Linear Modelling DC Characteristics Fit the Data very well Kink effects not included in the model RF Data (4x200 μm) EE-HEMT model generated from IC-Cap measurements Transferred to ADS and fitted to measured data

9. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 LNA SIMULATIONS The use of large inductors (generally used for input matching) on MMIC: Large space on chip Generate significant series resistance which greatly increases the noise figure Avoiding large inductors ?? No input matching? Off-chip components?

10. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 LNA SIMULATIONS Single stage LNA (800 um gate width) with no input matching

11. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 LNA SIMULATIONS Single stage LNA (800 um gate width) with no input matching @ 1.4 GHz NF < 0.6dB

12. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 LNA SIMULATIONS Single stage LNA (800 µm gate width) with off-chip components.

13. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 LNA SIMULATIONS Single stage LNA (800 µm gate width) with off-chip components. @ 1.4 GHz NF < 0.45dB

14. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 ADC Summary Comparator Design Transistor Type (mm 2 ) Power (mW) Power Saving (%) 1 st Generation 5 1,730- 2 nd Generation 5 5 (circuit) 1,20030 1.5 5 50271 3 rd Generation (folding) 1.5 535080 AIM: Design and fabrication of a 4bit 4GS/s ADC consuming 100 mW Current state-of-the-art : 0.18µm CMOS 4-bit 4GS/s - 220mW [1] FULL ADC Results to follow shortly. [1] S. Park, Y. Palaskas, and M. P. Flynn, "A 4GS/s 4b flash ADC in 0.18 m CMOS, IEEE Symp. On Circuits and Systems, pp 2330 – 2339, Feb 2006

15. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 ADC Basic Building Blocks Current work Basic Building blocks for the ADC designed using ADS Coplanar waveguide design Differential Amplifier Ex-Or/OR/AND Latch 12-Mask procedure HBT (9 masks) NiCr Resistors (~100 ohms/sq) 3 metal layers Polyimide dielectric EX-OR Complete MMIC

16. B. BOUDJELIDA 2 nd SKADS Workshop 10-11 October 2007 CONCLUSIONS Large periphery transistors are needed for low noise resistance Rn and wide band operation especially at low frequencies (< 2GHz). A wide range of large periphery multi-finger InGaAs/InAlAs pHEMTs have been fabricated (up to 1.2mm gate width). Accurate Linear and Nonlinear models have been obtained for these devices. Simulated LNA based on this design yield less than 0.45dB Noise figure at 1.4GHz even at 1µm gate length! 4 bit 4GS/s ADC designed, simulated and basic building blocks fabricated. LNA and ADC are being fabricated now.