1. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Gate Design n Static complementary logic gate structures. n Switch logic. n Other Gate issues

2. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Static complementary gates n Complementary –have complementary pullup (p-type) and pulldown (n-type) networks. n Static –do not rely on stored charge. n Advantage of Static complementary gates –Simple, effective, reliable; hence ubiquitous.

3. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Static complementary gate structure Pullup and pulldown networks: pullup Network(P type) pulldown Network(N type) V DD V SS out inputs

4. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Inverter n If the input voltage is '1' (VCC) – P-type transistor on top is nonconducting –N-type transistor is conducting and provides a path from GND to the output. –The output therefore is '0'. a out +

5. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR NAND gate + b a out

6. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR NOR gate + b a out

7. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR AOI/OAI gates n AOI –and/or/invert n OAI –or/and/invert. n Why ? –Implement larger functions. –Pullup and pulldown networks are compact: –smaller area, higher speed than NAND/NOR network equivalents. n AOI312 –and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

8. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR AOI example out = [ab+c]: symbolcircuit and or invert

9. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Pullup/pulldown network design n Pullup and pulldown –Networks are duals. n To design one gate –First design one network –Then compute dual to get other network. n Example: –design network which »pulls down when output should be 0 –then find dual to get pullup network

10. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Dual network construction dummy a bc a b c

11. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Switch logic n Can implement Boolean formulas –as networks of switches. n Can build switches –from MOS transistorstransmission gates. n Transmission gates –do not amplify but have smaller layouts.

12. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Switch logic network a b 0 1 about 00X 011 100 11X

13. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Another switch logic network a b r s about 00X 01r 10s 11X

14. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Switch-based mux

15. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Types of switches

16. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Behavior of n-type switch n-type switch has source-drain voltage drop when conducting: »conducts logic 0 perfectly; »introduces threshold drop into logic 1. V DD V DD - V t

17. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR n-type switch driving static logic Switch underdrives static gate, but gate restores logic levels. V DD V DD - V t

18. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR n-type switch driving switch logic Voltage drop causes next stage to be turned on weakly. V DD V DD - V t V DD

19. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Behavior of complementary switch n Complementary switch –Products full-supply voltages for both logic 0 and logic 1: »n-type transistor conducts logic 0; »p-type transistor conducts logic 1.

20. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Charge sharing n Values are stored at parasitic capacitances on wires:

21. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Charge sharing example 1 1 0 00 11

22. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR DCSL gate

23. FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR MTCMOS gate