1. Design Implementation Full Custom ICs, ASICs & PLDs ETEG 431 SG ASIC: Application Specific Integrated Circuit PLD: Programmable Logic Device FPGA: Field Programmable Gate Array _______________________________________ >> Buzzwords and Acronyms

2. Design Implementation To Build a Chip ETEG 431 SG Logic Design Circuit Design Physical Design Test Generation Fabrication Validation Many Different Layers

3. Design Implementation A CMOS Gate ETEG 431 SG

4. Design Implementation P Well (NMOS): As viewed from above ETEG 431 SG

5. Design Implementation Implementation Choices ETEG 431 SG Full-Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGAs) Array-based Semi-Custom Full-Custom Standard Cells Compiled Cells Macro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGAs) Full Custom ASIC PLD

6. Design Implementation Implementation Choices (Processes) ETEG 431 SG Full Custom: Run all processes Logical, Physical, Diffusion, Metal Gate Array (Sea of Gates): Change Metal Layer Logical, Simple Physical, Metal Standard Cell: Change all Layers Logical, Simple Physical, Diffusion, Metal PLD (FPGA) : Program Logical, Simple Physical

7. Design Implementation Implementation Choices (Time to Market) ETEG 431 SG 1. FPGA 2. Gate Array 3. Standard Cell 4. Full Custom

8. Design Implementation Implementation Choices (Cost) ETEG 431 SG Development cost (lowest to highest) FPGA Gate Array Standard Cell Full Custom Device cost (lowest to highest) Full Custom Standard Cell Gate Array FPGA

9. Design Implementation Implementation Choices (Typical Volume Concept) ETEG 431 SG

10. Design Implementation Implementation Choices (Time Critical Market Volume) ETEG 431 SG