1. RTL Design Methodology
Lecture 10
RTL Design Methodology
Sorting Example

2. Required reading P. Chu, FPGA Prototyping by VHDL Examples
Chapter 6, FSMD
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design
Chapter 10.2, Design Examples
ECE 448 – FPGA and ASIC Design with VHDL

3. Structure of a Typical Digital System
Data Inputs
Control & Status Inputs
Control
Signals
Datapath
(Execution
Unit)
Controller
(Control
Unit)
Status
Signals
Data Outputs
Control & Status Outputs

4. Hardware Design with RTL VHDL
Pseudocode
Interface
Datapath
Controller
Block
diagram
Block
diagram
State diagram
or ASM chart
VHDL code
VHDL code
VHDL code

5. Steps of the Design Process
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
ASM chart of the Controller
RTL VHDL code of the Datapath, the Controller, and the Top Unit
Testbench of the Datapath, the Controller, and the Top Unit
Functional simulation and debugging
Synthesis and post-synthesis simulation
Implementation and timing simulation
Experimental testing

6. Steps of the Design Process Practiced in Class Today
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
ASM chart of the Controller
RTL VHDL code of the Datapath, the Controller, and the Top Unit
Testbench of the Datapath, the Controller, and the Top Unit
Functional simulation and debugging
Synthesis and post-synthesis simulation
Implementation and timing simulation
Experimental testing

7. Sorting
example

8. Sorting - Required Interface
Clock
Resetn
DataIn N
DataOut
Done
RAdd L
WrInit S
(0=initialization
1=computations) Rd

9. Sorting - Required Interface

10. Simulation results for the sort operation (1) Loading memory and starting sorting

11. Simulation results for the sort operation (2) Completing sorting and reading out memory

12. Sorting - Example During Sorting 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2
After
sorting
Before
sorting
i=0 i=0 i=0 i=1 i=1 i=2
j=1 j=2 j=3 j=2 j=3 j=3
Address 1 2 3
Legend:
position of memory
indexed by i
position of memory
indexed by j Mi Mj

13. Pseudocode [load input data] [load input data] for i = to 2 do for i =
FOR k = 4
FOR any k ≥ 2
[load input data]
[load input data]
for i = to 2 do
for i = to k - 2 do A = Mi ; A = Mi ;
for j = i + 1 to 3 do
for j = i + 1 to k – 1 do B = Mj ; B = Mj ; if B
< A
then if B
< A
then Mi = B ; Mi = B ; Mj = A ; Mj = A ; A = Mi ; A = Mi ;
endif ;
endif ;
endfor;
endfor;
endfor;
endfor;
[read output data]
[read output data]

14. Pseudocode wait for s=1 for i=0 to k-2 do A = Mi for j=i+1 to k-1 do
B = Mj
if A > B then
Mi = B
Mj = A
end if
end for
Done
wait for s=0
go to the beginning

15. Block diagram of the Datapath
DataIn
RAdd
ABMux N L N L Li LD 1
Resetn s Ei EN
RST
CLK
Din s
Clock +1
Csel
WrInit We
DIN WE Lj LD
Addr L
Resetn Wr i Ej EN
RST
ADDR
CLK
Clock
CLK
Clock 1
DOUT L j L 1 N
Mij EA EB
= k-2
= k-1 EN
CLK
RST
Resetn EN
Resetn
RST
CLK
Clock
Clock Rd N N zi zj N 1
Bout A B
DataOut
A>B
Block diagram of the Datapath
AgtB

16. Interface with the division into the Datapath and the Controller
RAddr
DataIn
WrInit
Clock Rd
Resetn s N L
AgtB zi zj
Datapath
Controller Wr Li Ei Lj Ej EA EB
Bout
Csel N
DataOut
Done