1. RTL Design Methodology
Lecture 10
RTL Design Methodology
Sorting

2. Structure of a Typical Digital System
Data Inputs
Control Inputs
Control
Signals
Datapath
(Execution
Unit)
Controller
(Control
Unit)
Status
Signals
Data Outputs
Control Outputs

3. Hardware Design with RTL VHDL
Interface
Pseudocode
Datapath
Controller
Block
diagram
Block
diagram
State diagram
or ASM chart
VHDL code
VHDL code
VHDL code

4. Steps of the Design Process
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
ASM chart of the Controller
RTL VHDL code
Testbench
Debugging
Synthesis and implementation
Experimental testing

5. Steps of the Design Process Practiced in Class
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
ASM chart of the Controller
RTL VHDL code
Testbench
Debugging
Synthesis and implementation
Experimental testing

6. Sorting
Example

7. Sorting - Required Interface
Clock
Resetn
DataIn N
DataOut
Done
RAdd L
WrInit S
(0=initialization
1=computations) Rd

8. Simulation results for the sort operation (1) Loading the registers and starting sorting

9. Simulation results for the sort operation (2) Completing sorting and reading out registers

10. Sorting - Example During Sorting 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2
After
sorting
Before
sorting
i=0 i=0 i=0 i=1 i=1 i=2
j=1 j=2 j=3 j=2 j=3 j=3
address 1 2 3
Legend:
position of memory
indexed by i
position of memory
indexed by j i j

11. Pseudocode wait for s=1 for i=0 to k-2 do A = M[i] for j=i+1 to k-1 do
B = M[j]
if A > B then
M[i] = B
M[j] = A
end if
end for
Done
wait for s=0
go to the beginning