Presentation is loading. Please wait.

Presentation is loading. Please wait.

Manufacturing Testing

Published byGisle Caspersen Modified over 5 years ago

Similar presentations

Presentation on theme: "Manufacturing Testing"— Presentation transcript:

1 Manufacturing Testing

2 Manufacturing Testing
What is testing? Apply the input stimuli, test vector, to DUT Observe the response from DUT, and compare with expected results How? Fast and exact Automation

3 S HONG(POSTECH)

4 S HONG(POSTECH)

5 S HONG(POSTECH)

6 S HONG(POSTECH)

7 S HONG(POSTECH)

8 S HONG(POSTECH)

9 S HONG(POSTECH)

10 S HONG(POSTECH)

11 S HONG(POSTECH)

12 S HONG(POSTECH)

13 S HONG(POSTECH)

14 S HONG(POSTECH)

15 S HONG(POSTECH)

16 S HONG(POSTECH)

17 S HONG(POSTECH)

18 S HONG(POSTECH)

19 S HONG(POSTECH)

20 S HONG(POSTECH)

21 S HONG(POSTECH)

22 S HONG(POSTECH)

23 Fault Modeling Why model faults? Some real defects in VLSI and PCB
Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults Transistor faults Bushnell & Agrawal (KAP)

24 Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Bushnell & Agrawal (KAP)

25 Some Real Defects in Chips
Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) Time-dependent failures Dielectric breakdown Electromigration Packaging failures Contact degradation Seal leaks Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. Bushnell & Agrawal (KAP)

26 Occurrence frequency (%)
Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 8 5 Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. Bushnell & Agrawal (KAP)

27 Common Fault Models Single stuck-at faults
Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (p ) of the book. Bushnell & Agrawal (KAP)

28 S HONG(POSTECH)

29 S HONG(POSTECH)

30 S HONG(POSTECH)

31 S HONG(POSTECH)

32 S HONG(POSTECH)

33 S HONG(POSTECH)

34 S HONG(POSTECH)

35 S HONG(POSTECH)

36 S HONG(POSTECH)

37 Single Stuck-at Fault Three properties define a single stuck-at fault
Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value c j 0(1) s-a-0 a d 1(0) g 1 h z i 1 b e 1 k f Test vector for h s-a-0 fault Bushnell & Agrawal (KAP)

38 S HONG(POSTECH)

39 S HONG(POSTECH)

40 S HONG(POSTECH)

41 S HONG(POSTECH)

42 Scan Flip-Flop (SFF) D Master latch Slave latch TC Q MUX Q SD CK
Logic overhead MUX Q SD CK D flip-flop Master open CK Slave open t Normal mode, D selected Scan mode, SD selected TC t Bushnell & Agrawal (KAP)

43 Arbitrary Synchronous Sequencial Circuits
Combinational logic PI PO FF Not shown: CK or MCK/SCK feed all SFFs. Bushnell & Agrawal (KAP)

44 Adding Scan Structure Combinational logic PI PO SFF SCANOUT TC SCANIN
Not shown: CK or MCK/SCK feed all SFFs. SCANIN Bushnell & Agrawal (KAP)

45 Comb. Test Vectors I1 I2 O1 O2 PI PO Combinational logic SCANIN TC
SCANOUT S1 S2 N1 N2 Next state Present state Bushnell & Agrawal (KAP)

Download ppt "Manufacturing Testing"

Similar presentations

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt1 Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt1 Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence)
V. Vaithianathan, AP/ECE

V. Vaithianathan, AP/ECE
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.
Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.

Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.
Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.

Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.
CMP238: Projeto e Teste de Sistemas VLSI Marcelo Lubaszewski Aula 2 - Teste PPGC - UFRGS 2005/I.

CMP238: Projeto e Teste de Sistemas VLSI Marcelo Lubaszewski Aula 2 - Teste PPGC - UFRGS 2005/I.
March 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 211 Lecture 21 I DDQ Current Testing n Definition n Faults detected by I DDQ tests n Vector generation.

March 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 211 Lecture 21 I DDQ Current Testing n Definition n Faults detected by I DDQ tests n Vector generation.
Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 201 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay.

Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 201 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay.
Dec 21, Design for Testability Virendra Singh Indian Institute of Science Bangalore {computer, ieee}.org IEP on Digital System.

Dec 21, Design for Testability Virendra Singh Indian Institute of Science Bangalore {computer, ieee}.org IEP on Digital System.
Copyright 2001, Agrawal & BushnellDay-1 AM-3 Lecture 31 Testing Analog & Digital Products Lecture 3: Fault Modeling n Why model faults? n Some real defects.

Copyright 2001, Agrawal & BushnellDay-1 AM-3 Lecture 31 Testing Analog & Digital Products Lecture 3: Fault Modeling n Why model faults? n Some real defects.
Lecture 20 Delay Test (Lecture 17alt in the Alternative Sequence)

Lecture 20 Delay Test (Lecture 17alt in the Alternative Sequence)
Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.

Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.
1 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests  Non-robust test  Robust test  Five-valued.

1 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests  Non-robust test  Robust test  Five-valued.
1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.
Fundamentals of Digital Test and DFT

Fundamentals of Digital Test and DFT
ELEN 468 Lecture 241 ELEN 468 Advanced Logic Design Lecture 24 Design for Testability.

ELEN 468 Lecture 241 ELEN 468 Advanced Logic Design Lecture 24 Design for Testability.
Spring 08, Mar 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 VLSI Test Principles Vishwani D. Agrawal James.

Spring 08, Mar 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 VLSI Test Principles Vishwani D. Agrawal James.
Lecture 5 Fault Modeling

Lecture 5 Fault Modeling
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault.
1 Introduction VLSI Testing. 2 Overview First digital products (mid 1940's) Complexity:low MTTF:hours Cost:high Present day products (mid 1980's) Complexity:high.

1 Introduction VLSI Testing. 2 Overview First digital products (mid 1940's) Complexity:low MTTF:hours Cost:high Present day products (mid 1980's) Complexity:high.

Similar presentations

Ads by Google