1. Robert Brayton Alan Mishchenko Department of EECS UC Berkeley
Task ID: SAT-based Methods for Scalable Synthesis and Verification
Robert Brayton Alan Mishchenko
Department of EECS
UC Berkeley

2. Task Overview SRC task ID: 2710.001 Start date: 1-Nov-2016
Thrust area: CADT
Task leaders:
Robert K. Brayton, Univ. of California/Berkeley
Alan Mishchenko, Univ. of California/Berkeley
Industrial liaisons:
See next slide
Students:
Yen-Sheng Ho (graduated)
Kevin Cheang (joining in Fall 2019)

3. Industrial Liaisons IBM Intel Mentor (Siemens) Texas Instruments
Alexander Ivrii
Jason Baumgartner
Victor Kravets
Intel
Timothy Kam
Steven Burns
Michael Kishinevsky
Mentor (Siemens)
Jeremy Levitt
Texas Instruments
Devanathan Varadarajan
Venkatraman Ramakrishnan

4. Active Collaborators Discuss, publish, exchange visits with:
EPFL, Switzerland (group of Professor G. De Micheli)
Tokyo University, Japan (group of Professor M. Fujita)
Ritsumeikan University, Kyoto, Japan (group of Professor S. Yamashita)
UFRGS, Brazil (group of Professor A. Reis)
NTU, Taiwan (group of Professor R. Jiang)
CCU, Taiwan (group of Professor M. Lin)
Fudan University, China (group of Professor L. Wang)
UMass, Amherst (group of Professor M. Ciesielski)
HKUST, Hong Kong (group of Professor K.-T. Cheng)

5. Anticipated Results
Methodology and algorithms for next-generation improvements in logic synthesis, addressing
reverse engineering
SAT-based circuit restructuring
precomputation of properties for practical Boolean functions
Public software implementation of the above methodology and algorithms
Experimental evaluation on industrial benchmarks.

6. Responding to the Needs of SRC Companies
Reverse engineering enables word-level methods for gate-level problems
S3 System Tools
S3.4 Advanced logic/physical/high-level synthesis and cross-boundary optimization
Scalable synthesis leads to scalable verification
V1 Verification Core Technologies
V1.1 Advances in the scalability of automated model checking and sequential equivalence checking techniques for bit-level and bit-vector models
V1.2 Advances in techniques: general-purpose SAT solvers; constraint solving techniques; SAT solvers tuned for specific applications; automatic abstraction and abstraction-refinement; satisfiability modulo theories (SMT)
V1.3 Novel and improved algorithms for optimizing design and specification logic.
Computing test-suites for multiple-fault testing for different fault models
T1 Test Cost and Quality Improvement
T1.1 Test cost reduction
T1.4 Methods to improve test quality by effective test pattern selection across fault models
SAT-based formulations can contribute to other areas
S3.5 Fundamental/significant place/route improvements, including how to scale the methods for multi-core designs and reliability-aware place and route

7. Task Deliverables 31-Oct-2017
Software release of the RE engine and RE-enhanced equivalence checking engine. Evaluation on industrial problems.
31-Oct-2018
Software release of SAT-based logic restructuring. Evaluation on industrial problems.
31-Oct-2019
Software release of computation of Boolean properties with applications to network optimization. Evaluation on industrial problems.
Final report summarizing research accomplishments and future direction.

8. Background and Motivation
Reverse engineering
Discovering high-level structure in gate-level netlists
Useful for both verification and synthesis
SAT-based circuit restructuring
Global, incremental, and exhaustive
Useful for delay/area optimization before and after mapping
The “genome project” of logic synthesis
Precomputing useful functional properties of practical Boolean functions up to 16 inputs
For example, exhaustive enumeration of non-redundant circuit structures for small practical functions will be used
Useful for incremental resynthesis, approximate synthesis, FPGA architecture evaluation, etc

9. Summary of Recent Progress for Each Technical Goal
1st year: Reverse engineering
Presented two years ago
2nd year: SAT-based circuit restructuring
Presented last year
3rd year: The “genome project” of logic synthesis
Enumeration of minimum circuit structures for small Boolean functions (IWLS’19)
Fast adjustable NPN classification using generalized symmetries (ACM TRETS’19)
Scalable Boolean methods in a modern synthesis flow (DATE’19)
Scalable generic logic synthesis: One approach to rule them all (DAC’19)
On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis (DATE’19)
Follow-up towards solving technical goals from the previous years
Unlocking fine-grain parallelism for AIG rewriting (ICCAD’18)
Parallel combinational equivalence checking (IWLS’19)
Scaling-up ESOP synthesis for quantum compilation (ISMVL’19)
Rewriting environment for arithmetic circuit verification (LPAR’18)

10. Comparison with Existing Work
Enumeration of minimum circuit structures
Existing work (TAOCP, by Donald Knuth) determined functional complexity of small Boolean functions but did not count or derive minimum circuit structures
Improved methods for exact NPN classification
For the first time, it is possible to compute exact NPN class of functions up to 16 inputs (the worst-case runtime reduced from days to minutes)
Using precomputed structures
Improved quality of results in various applications dealing with logic synthesis, compared to previous work
Various extensions and improvements
- Application to rewriting of AIGs, XAGs, MIGs, LUT networks, etc
- Building a flow for quantum computing

11. Research Overview
The following slides present three most important research results since the last review
Enumeration of minimum circuit structures
Improved methods for exact NPN classification
New applications of precomputed structures

12. Result 1: Exhaustive Enumeration of Minimum Circuit Structures
The focus of our work is on
counting the number of different min-circuits
generating all different min-circuits
Reproduced and independently verified statistics published by Donald Knuth on the minimum circuit complexity of all 3-, 4-, 5-input functions
For the first time, computed all minimum circuits for 3-, 4-, 5-, and (some of the) 6-input functions
Takes 0.01 sec for all 4-input functions
Takes 200 sec for all 5-input functions
S.-Y. Lee, J.-H. R. Jiang, A. Mishchenko, and R. Brayton, "Enumeration of minimum circuit structures", Submitted to IWLS'19.

13. Two Different 12-Node Min-Circuits for The Most Complex 5-Function: 169ae443

14. NPN Classes
Two functions belong to the same NPN class if one of them can be derived from the other by complementing inputs (N), permuting inputs (P), and complementing the output (N)

15. Computing L(f) for 5-Functions
This table is generated using command “funenum –I 5 –l” in ABC.

16. Distribution of Min-Circuit Counts for 5-Functions
It is interesting to note that among all 11-node NPN classes, there are 5450 classes with a unique min-circuit and one class with exactly 523 different min-circiuts. The next closest to it, is one class with exactly 314 different min-circuits.

17. Result 2: Improved Methods for NPN Classification
The need for NPN classification is two-fold:
Functional enumeration requires exact classification
Pre-computation-based use-cases require heuristic one
During the last year, we improved both
New heuristic classification ( ‘testnpn –A 9’ in ABC) is about 3x faster than the previous best
New exact classification ( ‘testnpn –A 11’ in ABC) is about x faster than the previous best
Novel methods are used in both (see references)
X. Zhou, L. Wang, and A. Mishchenko, "Fast adjustable NPN classification using generalized symmetries“. To appear in ACM TRETS. 17

18. Result 3: Novel Applications of Precomputed Structures
Used exact synthesis and/or precomputed structures in a number of practical applications:
Logic restructuring for simple circuit structures
AIG, XAG, MIG, XMG, etc
Logic restructuring for LUT networks
Potential applications in approximate logic synthesis
Potential applications in FPGA architecture evaluation
Demonstrated improvements over past methods
for example, [DATE’19] shows 5.5% (4.0 %) reductions for 3-LUT (4-LUT) networks
H. Riener, W. Haaswijk, A. Mishchenko, G. De Micheli, and M. Soeken, "On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis", Proc. DATE'19. 18

19. Relevant Recent Publications
“Genome of logic synthesis”
- S.-Y. Lee, J.-H. R. Jiang, A. Mishchenko, and R. Brayton, "Enumeration of minimum circuit structures", Submitted to IWLS'19.
Improved exact NPN classification
- X. Zhou, L. Wang, and A. Mishchenko, "Fast adjustable NPN classification using generalized symmetries", To appear in ACM TRETS.
- X. Zhou, L. Wang, and A. Mishchenko, “Fast exact NPN classification by co-designing the canonical form and its computation”, To be submitted.
Applications of exact logic synthesis
- E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, Ch. Casares, P.-E. Gaillardon, and G. De Micheli, "Scalable Boolean methods in a modern synthesis flow", Proc. DATE'19.
- H. Riener, W. Haaswijk, A. Mishchenko, G. De Micheli, and M. Soeken, "On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis", Proc. DATE'19.
- H. Riener, E. Testa, W. Haaswijk, M. Soeken, L. Amaru, A. Mishchenko, and G. De Micheli, "Scalable generic logic synthesis: One approach to rule them all", DAC'19.
Other applications
- V. N. Possani, Y.-S. Lu, A. Mishchenko, K. Pingali, R. Ribas, and A. Reis, "Unlocking fine-grain parallelism for AIG rewriting", Proc. ICCAD'18.
- V. N. Possani, A. Mishchenko, R. Ribas, and A. Reis, "Parallel combinational equivalence checking", Submitted to IWLS'19.
- B. Schmitt, M. Soeken, A. Mishchenko, and G. De Micheli, "Scaling-up ESOP synthesis for quantum compilation", Submitted to ISMVL'19.

20. Conclusions Reviewed the SRC task (the final year)
“SAT-based Methods for Scalable Synthesis and Verification”
Discussed ongoing and forthcoming work
Reviewed recent publications