1. Dave Judd Kathy Yelick Computer Science Division UC Berkeley
Compiling for VIRAM
Dave Judd
Kathy Yelick
Computer Science Division
UC Berkeley
4/28/2019

2. VIRAM Compiler Based on Cray Inc production compiler
Used on the T90, C90, as well as the T3D and T3E
Being ported by Cray Inc to the SV2 architecture
C, C++, and Fortran 95 front-ends
Fortran not supported in VIRAM
Extensive vectorization, restructuring capability
VIRAM code generator based on new SV2 code generator
SV2 code gen being developed in parallel w/ VIRAM
SV2 vector architecture similar to VIRAM
4/28/2019

3. VIRAM Compiler Status Frontends Optimizer Code Generators C T3D/T3E
PDGCS
C90/T90/SV1
Fortran95
SV2/VIRAM
VIRAM vector & MIPS scalar support
Compiles & executes C & C++ commercial test suites
Compiles and executes several Cray vector C test suites
4/28/2019

4. Progress Since Winter Retreat
“-n32” ABI implemented, replacing “–64”
C++ support, modena test suite
Code scheduler
Code cleanup for vl, mvl, vbase, vinc registers
Sync support partially implemented
Addl. “vector4” test suite executes correctly
Eliminate dependency on Cray include files
Vectorize loops w/ 8, 16 bit data
A “few” bugs fixed
4/28/2019

5. Compiler Testing C regression test suite (commercial test suite)
Scalar emphasis, C conformance
All tests pass except:
Small numerical differences due to lack on 128 f.p. support
C++ test suite
1167 of 1183 tests execute correctly.
12 failures in compilation: “undefined variables”
4 failures in execution: bad answers
4/28/2019

6. Compiler Testing Vector regression test suites (CRAY)
Specifically tests for vectorization
Compares vector and scalar results
Easy to isolate problems
“vector” status:
59 of 62 tests pass
Some minor numerical differences
1 bad answer, 2 integer overflow
“vector4” status
163 of 165 tests execute correctly
1 bad anwer, 1 illegal use of vector inst.
4/28/2019

7. Kernel Performance: mvm matrix-vector multiplication
64x64, 32 bit floating pt.
Hand optimized assembly code
579 mflops
vcc w/ restrict keywords added
352 mflops
+ 1 element padding to avoid bank conflicts
401 mflops
+ shortloop directive
Loops interchanged & outer loop vectorized by vcc.
592 mflops
4/28/2019

8. Mods to mvm code /* Original code mvm.c */ /* Modified code */
void mvm (float * A, void mvm (float * restrict A, float * X, float * restrict X, float * Y, float * restrict Y, int n, int n, int acol ) { int acol ) { int i,j; int i,j; float x_elem < if ( n <= 64 ) { if ( n <= 64 ) { for (i = 0; i < n; i++) { for (i = 0; i < n; i++) { #pragma shortloop for (j = 0; j < n; j++) { for (j = 0; j < n; j++) { Y[j] += A[j*acol+i] * x_elem; Y[j] += A[j*acol+i] * X[i]; } } } } } } } }
4/28/2019

9. Kernel performance: mm_mul matrix –matrix multiplication
64x64x64, 32 bit float, 1.6 gigaflop theoretical peak
Hand coded assembly
mm-mul-small.s
1.58 gigaflops
vcc w/ restrict and shortloop keywords
0.852 gigaflops
+ inner two loops in separate function, allows outer loop vectorization
1.51 gigaflops
4/28/2019

10. Kernel performance: saxpy
32 bit floating point ops
N=64
256
1024
4096
Hand coded assembly
vcc w/restrict keywords
379
593
691
720
385
596
692
721
4/28/2019

11. Kernel performance: motion_estimate
32 bit integer ops, finding the minimum sum of absolute differences for a reference block and a region in an image.
Hand optimized assembly
1.181 gigaops
vcc w/restrict keywords
170 mops
+ shortloop directives
253 mops
+ outer loop unroll directive
257 mops*
*No improvement because of spilling.
4/28/2019

12. Dongarra loops 100 loops to test compiler vectorization capability
Rewritten in C by Cray (?)
vcc vectorizes 74 loops
vcc partially vectorizes 3 loops
vcc conditionally vectorizes 3 loops
1 loop not vectorized because vector sin/cos not currently available on viram.
19 other loops not vectorized
Data provided by Sam Williams
4/28/2019

13. Features Remaining: Support version 3 isa and version 4 isa:
Isa changes required by Mips Inc. scalar core
Performance simulator only supports “old”isa
Finish sync support
take advantage of Cray implementation
VIRAM machine “target”
Allow easier maintainence of frontend and optimizer mods for viram
User documentation
Summary of differences w/Cray compiler
Useful options, hints for vector code
4/28/2019

14. Performance Features Remaining
Additional tuning: instruction scheduler
Support new SV2 inliner for C/C++
Shortloop enhancements
Reduce spilling
Scheduler concern with registers
Ordering of blocks for register assignment within “priority groups”
Special vector registers carried across calls
Loop unrolling for vector loops
Tune for key benchmarks
4/28/2019

15. Other Future Compiler Features ?
Support for speculative execution
Compiler extensions for fixed point hardware
Support for vector functions; vector mlib
4/28/2019

16. Summary vcc is a reasonably robust compiler for VIRAM
Performance on kernels is good w/appropriate directives, some effort for optimum vectorization
Need to prioritize remaining work
4/28/2019

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22. Backup slides follow
4/28/2019

23. Vector Architectural State
VP0
VP1
VPvl-1
vr0
vr1
vr31
vpw
Data
Registers
Virtual Processors (vl)
Number of VPs given by the Vector Length register vl
Width of each VP given by the register vpw
vpw is one of {8b,16b,32b,64b}
Maximum vector length is given by a read-only register mvl
mvl depends on implementation and vpw: {128,128,64,32} in VIRAM-1
4/28/2019

24. Codegen/optimizer issues for VIRAM
Variable virtual processor width (VPW)
Variable maximum vector register length (MVL)
Vector flag registers treated as 1 bit wide vector register
Multiple base, incr, stride regs. + autoincrement
Fixed point arithmetic (saturating add, etc.)
Memory consistency
New vector instructions not available on SV2
4/28/2019

25. Generating Code for Variable VPW
Strategy: vectorizer determines minimum correct vpw for each loop nest
Vectorizer assumes vpw=64 initially
At end of vectorization, discard vectorized copy of loop if greatest width encountered is less than 64 and start vectorization over with new vpw.
Code gen checks vpw for each loop nest.
Limitation: a single loop nest will run at the speed of the widest type.
Reason: simplicity & performance of the common case
No attempt to split/combine loops based on vpw
4/28/2019

26. Generating Code for Variable MVL
Maximum vector length is not specified in IRAM ISA.
However, compiler assumes mvl at compile time
mvl based on vpw
mvl assumption dependent on VIRAM-1 hardware implementation
Recompiling required for future hardware versions if mvl changes
MVL knowledge useful for code gen and vectorizer:
register spilling
short loop vectorization
length-dependent vectorization ( and may eliminate safe vector length computation at run time)
for (i = 0; i < n; i=++)
a[i] = a[i+32]
4/28/2019

27. Memory consistency Sync instructions: SaV VaS VaV vp RaW WaR WaW
4/28/2019

28. VIRAM Tools vas: assembler vdis: disassembler vsim-isa: simulator
vsim-db: debugger
vsim-p: performance simulator
vsim-sync:memory consistency simulator
4/28/2019

29. vsim-sync Intended for debugging and optimizing sync’s
Tells you when there is a data hazard (sync needed)
Tells you when a sync executed that didn’t prevent a hazard;
sync may not be needed
according to dynamic execution
sync may be needed on some other execution path
4/28/2019