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4EY-07 Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Gates
Yuki Yamanashi, I. Okawa, N. Yoshikawa Yokohama National University (YNU) Aug. 5, 2010.
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Table of Contents Background
Implementation method of dynamically reconfigurable SFQ logic devices Implementation method Dynamically reconfigurable JTL/DFF circuit Dynamically reconfigurable AND/OR gate Variable bit-length shift register Conclusion
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Background Reconfigurable logic device Programmable logic array (PLA)
Field programmable gate array (FPGA) FPGA-like SFQ Circuit Fourie et al., IEEE TAS 17 (2007) 538.
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Motivation Reconfigurable SFQ devices previously implemented
Characteristic modulation by external dc control current Not suitable for high-speed operation Dynamically reconfigurable SFQ devices
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Table of Contents Background
Implementation method of dynamically reconfigurable SFQ logic devices Implementation method Dynamically reconfigurable JTL/DFF circuit Dynamically reconfigurable AND/OR gate Variable bit-length shift register Conclusion
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“Statically” Reconfigurable JTL/DFF Circuit
Ib clk JTL-mode (din -> dout) Ib din dout DFF-Mode 7.9 pH 169 mA
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“Dynamically” Reconfigurable JTL/DFF Circuit
NDRO Set_to_jtl Set_to_dff DFF
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Operation Principle JTL/DFF Circuit
JTL-mode (din -> dout) Set_to_jtl Set_to_dff Ib Set_to_jtl input DFF Initial state Ib DFF-Mode
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Simulation Result JTL/DFF Circuit
JTL mode DFF mode set_to_jtl set_to_dff clk din dout Time (ps) Simulated dc bias margin: 74% - 126%
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Reconfigurable JTL/DFF Cell
NDRO 80 mm SRL 2.5 kA/cm2 Nb Standard Process DFF
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Measured Waveform JTL/DFF Circuit
Measured dc bias margin: 72% - 107%
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Measurement Results JTL/DFF Circuit
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Dynamically Reconfigurable AND/OR Gate
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Simulation Result AND/OR Gate
OR-mode AND-mode Set_to_or Set_to_and A B CLK DOUT Time (ps) Bias Margin: 89% - 127%
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Table of Contents Background
Implementation method of dynamically reconfigurable SFQ logic devices Implementation method Dynamically reconfigurable JTL/DFF circuit Dynamically reconfigurable AND/OR gate Variable bit-length shift register Conclusion
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Variable Bit-Length Shift Register (SR)
Control circuit for pipelined processor Bit-shifter for floating point calculation Dynamically reconfigurable JTL/DFF circuit Set_to_jtl Set_to_dff
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Measurement Results 4-bit Variable Bit-Length SR
1-bit mode 3-bit mode Clock_input Data_input Data_output 3-bit shift 1-bit shift Dc bias margin: 71% - 91%
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Conclusion Investigation of implementation method of dynamically reconfigurable SFQ logic devices Implementation of the reconfigurable devices Reconfigurable JTL/DFF circuit AND/OR gate, NAND/NOR gate Demonstration of operation of variable bit-length shift register composed of dynamically reconfigurable SFQ logic devices
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