1. Speaker: Yumin Adviser: Prof. An-Yeu Wu Date: 2013/10/24
102-1 Under-Graduate Project Final Project : Single-path Delay Feedback FFT
Speaker: Yumin
Adviser: Prof. An-Yeu Wu
Date: 2013/10/24

2. IDFT/DFT & IFFT/FFT DFT IDFT
Definition of Discrete Fourier Transform (DFT) and Inverse DFT (IDFT)
Fast Fourier Transform (FFT) is based on the concept of “Divide-and-Conquer”.
DFT
x[n]
Time domain
sequence
X[k]
Frequency domain
spectrum
IDFT
Twiddle factor :
[1]

3. Radix-2 Butterfly of DIT & DIF
DIT : Decimation in time
DIF : Decimation in frequency
xi-1(k)
xi-1(m)
Xi(m)
Xi(k)
Twiddle factor Wn -1
xi-1(k)
xi-1(m)
Xi(k)
Xi(m)
Twiddle factor Wn -1

4. 8-Point FFT DIT Signal Flow
DFT-4
DFT-2
Bit-reverse order
Normal order
000
100
010
110
001
101
011
111
000
001
010
011
100
101
110
111
[1]

5. 8-Point FFT DIF Signal Flow
DFT-2
DFT-4
Normal order
Bit-reverse order
000
001
010
011
100
101
110
111
000
100
010
110
001
101
011
111
[1]

6. Hardware Implementation of FFT
Fully Spread
Reuse of Single Butterfly
Slow  Speed  Fast
Small  Area  Large
Complex  Control  Simple

7. Radix-2 Single-path Delay Feedback for N=16
[2]

8. Relationship of Radix-4 & Radix-22
BF4
BF2i
BF2ii
[2]

9. Radix-22 Single-path Delay Feedback for N=256
BF2i 1
Xr(n)
Xi(n)
Xr(n+N/2)
Xi(n+N/2)
Zr(n)
Zi(n)
Zr(n+N/2)
Zi(n+N/2) -
Xi(n+N/2)
Xr(n+N/2) t s
BF2ii 1
Xr(n)
Xi(n)
Zr(n)
Zi(n)
Zr(n+N/2)
Zi(n+N/2) -
[2]

10. Project Topic - FFT Topic: Single-path Delay Feedback FFT 期中報告: 11/21
Study of Algorithm
Behavior Model of FFT (C++ or Matlab)
Architecture Design and Analysis
Floating Point Modeling
Fixed-point Analysis
期末報告: 1/09
More Architecture Design and Analysis
Implementation by Verilog

11. Specification of FFT Requirements for 64-point FFT Evaluation Equation
Input data : 9+1-bit pure signed fraction
Number of bits for output data : Designed-defined
Number of bits for twiddle factor : Designer-defined
SQNR ≧ 50dB
Pass the test data provided
Evaluation Equation
Score = Area * (executoin time)2
The lower score, the higher performance

12. Optimal set: 2+6 = 8
Integer 2 bits
Fractional 6 bits
Fixed twiddle

13. Optimal set: 9+2 = 11
Integer 2 bits
Twiddle 9 bits
Fix Fractional

14. Optimal set: 9+7 = 15
Twiddle 9 bits
Fractional 7 bits
Fix Integer

15. Fractional 7 bits, Twiddle 9+1 bits

16. References
[1] Alan V.Oppenheim, Ronald W. Schafer, ”Discrete-time signal processing” 2nd edition.
[2] Shousheng He and Torkelson, M.,”A new approach to pipeline FFT processor,” Proceedings of IPPS '96, April 1996, pp766 –770.