1. The ESA MUSIC Project Breadboard HW Partitioning and ASIC Design Advanced Mobile Satellite Systems & Technologies presentation days ESA./ESTEC – 14-15 November 2000

2. AMSST Presentation Days – 14-15 November 2000 Outline MUSIC Receiver Implementation –MUSIC RX FPGA Complexity –FPGA Design Flow –HW/SW Partitioning EC-BAID ASIC –ASIC Design Flow –ASIC Architecture –ASIC Features

3. AMSST Presentation Days – 14-15 November 2000 MUSIC RX Functional Block Diagram

4. AMSST Presentation Days – 14-15 November 2000 MUSIC RX Implementation AD S807 FPGAs - ALTERA 10K100 ST 18952 DSP ASIC ADC DCO I Q N-stage Integrator Decimation In-Phase Front-End N-stage Comb Compensation Filter / CMF CIC f s f s f d f d =4R c f ˆ N-stage Integrator Decimation Quadrature Front-End N-stage Comb Compensation Filter / CMF CIC f s f s f d f s f s 2 n s =4 Interp. n s =2 2R c f d =4R c 2 n s =4 Interp. n s 2R I/Q Soft Data L CCTU CCAU Prompt-I Prompt-Q E/L-I E/L-Q E/L EC-BAID Unit I/Q Correlator FED Pilot Channel Code Traffic Channel Code Demux-I Demux-Q R c R c R s R s SNIR Estimation SNIRR s Symbol Start Signal Detect / Demod. Enable AFC Loop Filter Int. Clock 8R c IF Input f IF =70 MHz R c R c R c Code epoch Sync AGC Symb. Clock BER Measurem. P Interface BER f s IFd =4.464 MHzf

5. AMSST Presentation Days – 14-15 November 2000 AD S807 FPGAs - ALTERA 10K100 ST 18952 DSP MUSIC RX Implementation (Intermediate)

6. AMSST Presentation Days – 14-15 November 2000 MUSIC RX FPGA Design Flow Requirement FORTRAN Floating Point Model FORTRAN Simulation FORTRAN Test Bench OK? yes no FORTRAN Bit True Model FORTRAN Simulation OK? yes no VHDL RTL Model VHDL Simulation OK? yes no Macro Cell (RAM, ROM) VHDL Model VHDL Test Bench VHDL RTL Model Logic Synthesis VHDL FPGA Gate Level Netlist VHDL Gate Level Simulation OK? yes no OK? yes no Device Programming VHDL Test Bench ALTERA Library Synthesis Constraints ALTERA Library Device Fitting Interconnection Delay VHDL FPGA Gate Level Netlist VHDL Gate Level Simulation OK? yes no VHDL Test Bench ALTERA Library

7. AMSST Presentation Days – 14-15 November 2000 MUSIC RX FPGA Complexity

8. AMSST Presentation Days – 14-15 November 2000 MUSIC RX FPGA Partitioning

9. AMSST Presentation Days – 14-15 November 2000 MUSIC RX Implementation (Intermediate) AD S807 FPGAs - ALTERA 10K100 ST 18952 DSP 1st 2nd 3rd/4th

10. AMSST Presentation Days – 14-15 November 2000 PROGRAMMING FLAT CABLE CONNECTION BY FLAT CABLE 1st CPLD 2nd CPLD 3rd CPLD 4th CPLD PROTEO #1 PROTEO #2 MUSIC RX Implementation (Intermediate)

11. AMSST Presentation Days – 14-15 November 2000 1st CPLD 2nd CPLD 3rd CPLD 4th CPLD PROTEO #1 PROTEO #2

12. AMSST Presentation Days – 14-15 November 2000 MUSIC RX Implementation (Final) PROGRAMMING FLAT CABLE EC-BAID extra CPLD CONNECTION BY FLAT CABLE 1st CPLD 2nd CPLD EC-BAID ASIC PROTEO #1 EC-BAID BOARD

13. AMSST Presentation Days – 14-15 November 2000 EC-BAID ASIC Design Flow Requirement FORTRAN Floating Point Model FORTRAN Simulation FORTRAN Test Bench OK? yes no FORTRAN Bit True Model FORTRAN Simulation OK? yes no VHDL RTL Model VHDL Simulation OK? yes no Macro Cell (RAM, ROM) VHDL Model VHDL Test Bench VHDL RTL Model Logic Synthesis Synthesis Constraints VHDL Gate Level Netlist VHDL Gate Level Simulation ST HCMOS7 Library OK? yes no OK? yes no EC-BAID ASIC Back-End VHDL Post-Layout Simulation OK? yes no EC-BAID ASIC Foundry Run VHDL Test Bench ST HCMOS7 Library VHDL Test Bench ST HCMOS7 Library Parasitic Delay

14. AMSST Presentation Days – 14-15 November 2000 The MUSIC core: EC-BAID 1/3

15. AMSST Presentation Days – 14-15 November 2000 The MUSIC core: EC-BAID 2/3

16. AMSST Presentation Days – 14-15 November 2000 Correlation Receiver The MUSIC core: EC-BAID 3/3 1/T c s s y i e c 1,i 1/T c L 1 L 3 1 3/T c 1/T s + + 3/T c c MUX3 MUX2 b 1 AGC loop ( )*. b 1 ' 3/T c mem control mux control 1/T s 3/T c + - (1-F) c 1,i 1/T s 3/T c c x 1,w n.o. x 1,w + - ++ () x n.o. · c 1 L c 1,i hardware-multiplexing area Y RAM 128 x 42 X RAM 384 x 46

17. AMSST Presentation Days – 14-15 November 2000 EC-BAID Bit-true Simulation WH=E-GOLD sequences L=32 ideal chip timing and carrier frequency/phase recovery asynchronous MAI with evenly-distributed delays on one symbol period adaptation step = 2 -13 or 2 -15 N=L/2 active users with C/I=-6 dB each

18. AMSST Presentation Days – 14-15 November 2000 Shortened Programmable Observation Window Optimization of the EC-BAID: Window Length 1/2 y1y1 y0y0 y -1 Maximum Observation Window (3L chips) wCwC wCwC

19. AMSST Presentation Days – 14-15 November 2000 Optimization of the EC-BAID: Window Length 2/2 Optimum Length: 2 symbol intervals (0.5+1+0.5)

20. AMSST Presentation Days – 14-15 November 2000 The EC-BAID Long-term BER Drift

21. AMSST Presentation Days – 14-15 November 2000 Adaptive EC-BAID with Leakage Standard EC-BAID Leakage factor EC-BAID with Leakage

22. AMSST Presentation Days – 14-15 November 2000 Leak Factor Optimization

23. AMSST Presentation Days – 14-15 November 2000 ST HCMOS7 0.25 m Technology Key Features –2.5 V operating voltage, 3.3 V I/O –Gate Density: 35 Kgates/mm 2 –500 MHz systems clock –6 levels of metal with minimum enclosures, stacked contacts and VIAs –Ultra low power dissipation: 0.1 W/MHz/gate/std load –In production since June 1998

24. AMSST Presentation Days – 14-15 November 2000 EC-BAID ASIC Results

25. AMSST Presentation Days – 14-15 November 2000 EC-BAID ASIC pinout STM & TEAM EC-BAID INPUT SYNC. INPUT DATA CONFIG TESTING OUTPUT DATA OUTPUT SYNC. MONITOR

26. AMSST Presentation Days – 14-15 November 2000 EC-BAID ASIC pinout cont.

27. AMSST Presentation Days – 14-15 November 2000 EC-BAID ASIC Layout RAM 384 x 46 RAM 128 x 43 2 mm 2

28. AMSST Presentation Days – 14-15 November 2000 EC-BAID ASIC Main Features Robust Blind Interference Mitigation Detector ASIC – Programmable Code Length: L=32, 64 and 128 – 5 Mchip/sec Maximum Chip Rate – Programmable Convergence Speed – Low complexity: 27 Kgates + 23 Kbit RAM – Low power consumption: 45 mW @ 16 MHz clock - 2 Mchip/s – Reduced I/O pin number: 47 Embedded Phase Recovery Unit – Switchable on/off – Programmable Loop Filter Parameters (BW and DF) – Programmable Lock Detector ASIC Design-reuse approach allows for: – re-design to meet other system specification: higher chip rates, different I/O interfaces, etc. – re-targeting to different silicon technologies as ASSP – integration in more complex System-on-Chip design