1. 1 System Level Verification of OCP-IP based SoCs using OCP-IP eVC Himanshu Rawal eInfochips, Inc.,4655 Old Ironsides Drive, Suite 385,Santa Clara, CA 95054 Phone: +1-408-496-1882 e-mail: himanshu.rawal@einfochips.com

2. Confidential2 Agenda Introduction Brief on OCP Technology Benefits OCP IP eVC System Under test Block level verification System level verification Conclusion

3. Confidential3 Introduction SoC designs of todays world consists of different IP cores System designs today are extremely large and complex –Separate teams for architecture, hardware, and software Functional verification for such complex SoCs amounts to a significant portion in the total verification effort. –A divide & conquer approach is a necessity

4. Confidential4 The Verification Gap Traditional approach using ad-hoc verification methodology have run out of steam Verifying spec-adherence for multiple abstraction levels –High-level model, RTL, Gate-level, Hardware prototype, Silicon –Each level requires a different execution engine

5. Confidential5 Bridging the Verification Gap Successful system level verification –Successful functional verification of the block level interfaces Block level monitors –Flexibility of the verification environment Permit reuse of block level monitors to scale to the system level –Verification environment should have Very good debugging capacity Sufficient controllability Should be able to scale across various verification stages

6. Confidential6 Brief on OCP IP Technology Prominent design interconnect technologies of today's world Provides advantages like –Core Reusability, because it has clear and adaptable design boundaries –High Throughput, because of features like Multi Threading and bursts –Design Optimization, because you may choose to use only those OCP-IP features needed by the IP/Core –Simplified verification, because of the definite interface around each core

7. Confidential7 OCP IP eVC OCP eVC (e language Verification Component) –compliance with Open Core Protocol Specification 1.0 and 2.0 Release Candidate. –verification of DUT having master and/or slave OCP interface(s). –Provides with predefined generation, checking, and coverage capabilities –User can customize generation, checking, and coverage for special DUT needs –Full compliance with Verisitys e reuse methodology (eRM)

8. Confidential8 OCP IP eVC – Block Diagram

9. Confidential9 System Under Test Multi-million gate DSP VoP(Voice over Packet) SoC 3 DSP processors to process voice packets one MIPS processor for control functions, a large on-chip memory of packet storage Sonicss Inc. silicon backplane® (SB) bus is used for data transfers between all of the cores The interfaces have DMA engines attached to them on the bus- side to transfer the data back and forth from the memory All cores are connected to the SB OCP IP compatible interfaces External world interfaces to the SoC are Ethernet, SONET and PCI-X

10. Confidential10 System Under Test System On Chip DSP 0 DSP 1 DSP 2 MIPS® processor SONET D M A PCI-X D M A MII (Ethernet) DMA Silicon Backplane Micro Network OCP compliant interface

11. Confidential11 Block Level Verification Ethernet eVC and OCP eVC configured with active agents to drive and to respond to the stimuli from the MII IP core. Ethernet MAC core block with OCP IP interface

12. Confidential12 Block Level Verification - configuration Configuration of the OCP eVC //Assigning the name to the environment. extend ei_ocp_env_name : [OCP_MII_DMA]; //keep the environment to act as both master as well as slave. extend OCP_MII_DMA ei_ocp_env_u { keep env_kind == MASTER_AND_SLAVE; }; extend ei_ocp_agent_u { //keep agent in ACTIVE mode i.e. it can collect as well as inject data to the DUT. keep active_passive == ACTIVE; //hdl path should be hierarchical path of DUT top. keep hdl_path() == "~/ethernet_mii.ocp_dma_dut"; };

13. Confidential13 Block level to System Level Verification Simple and scalable –OCP IP eVC is now configured with a passive agent –Only monitoring OCP interface –Identify protocol errors –Collect functional coverage –Log OCP transfers and bursts for statistical purposes.

14. Confidential14 System Level Verification – eVC Configuration eVC configuration –The block level environment is scaled to system level by minimally changing configuration of the eVC extend ei_ocp_agent_u { //keep agent in PASSIVE mode It can only collect data to/from the DUT. keep active_passive == PASSIVE; //hdl path should be hierarchical path of DUT top. keep hdl_path() == ~/VoP_SoC_env.VoP_SoC_dut.ethernet_mii.ocp_dma_dut"; };

15. Confidential15 System Level Verification – Test generation Test generation –Generating different sequences, used for block level using virtual sequences extend comm_sequence_driver { sonet: sonet_master_sequence_driver; ethernet: ethernet_sequence_driver; pci-x: sonet_master_sequence_driver; }; extend comm_subsystem_unit { driver: comm_sequence_driver is instance; // Constrain the subdrivers. keep driver.sonet == sonet_unit.driver; keep driver.ethernet == ethernet_router_unit.driver; keep driver.pci-x == pci-x_unit.driver; };

16. Confidential16 System Level Verification

17. Confidential17 Conclusion OCP-IP compliant cores is an answer to the growing problem of compatibility between the SoC block cores eInfochips OCP IP eVC equipped with the methodologies like eRM and CDV can become an important tool for verifying OCP-IP based SoCs

18. Confidential18 Reference OCP Specification 1.0, OCP Specification 2.0 Release Candidate e language reference manual version 4.2. eRM(e Language Reuse Methodology) manual version 4.2. Vadvisor www.verificationvault.com