1. ECE 352 Digital System Fundamentals
SRAM Arrays
In this video, we will look at how we can use arrays of SRAM devices to implement a memory system with greater capacity than the device itself.

2. SRAM Device Characteristics
The device capacity is the total number of bits stored
The width is number of bits stored at each location
The depth is the number of locations that it contains
Example:
The 64k × 8 device below has a capacity of 512 kbits
indicates output
is tristated if CS=0
But first, let’s review some SRAM characteristics. The capacity of a memory is the number of bits it can store. The width of a memory is the number of bits at each location, which is also the memory word size. The depth of a memory is the number of locations in the memory. A memory with an N-bit address can have up 2^N locations. The example device shown here has a depth of 64k, and a width of 8 bits. Each location can store a single byte, and the device has a capacity of 512 kilobits. The device has 16 address lines, since 2^16 is 64k. The chip select input is a master enable signal for the device – the chip select must be asserted to perform any operation on the device. We will selectively enable only the desired devices in an array using their chip select inputs. The data output has tristate drivers, symbolized by the triangle. When the device is not selected, the output drivers are in the high-impedance state. This means that we can directly connect multiple devices’ data outputs together if we ensure that only one device will ever be enabled at any time.

3. Arrays of SRAM Devices
Can build an m × n SRAM memory system we need out of multiple, smaller SRAM devices
Key ideas:
Use multiple devices to create required memory capacity
Distribute words (or parts of words) across several devices
Need to be able to access all bits of the correct word at once
When we need more capacity than the available SRAM devices provide, we can combine an array of SRAM devices to create a memory system with greater capacity. We may need greater depth than the individual devices, greater width, or both. To do this, we will distribute words across multiple devices. Of course, we need to ensure that the memory array works correctly – that is, we need to be able to read and write each memory location. We also need to make sure that an address refers to the same location whether we are reading or writing, so that we can properly retrieve information that we’ve stored. We will look at a number of examples based on the 64k x 8 device shown here.

4. Increasing Width: 64k × 16 Array
The available 64k × 8 SRAM devices are deep enough, but they are not wide enough
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Each SRAM device stores half of each word.
In the first example, we want to have a memory system that can store 64k 16-bit words. The devices we have are deep enough—they have 64k locations—but they are only 8-bits wide. We being by creating an outer wrapper that contains the signals that will be inputs to the memory array. Note that the array has a 16-bit address, and 16-bit data ports. These numbers are based on the desired characteristics for the array, not the devices we use to build it. Since this array needs twice the capacity of a single device, we will need two devices. Each device stores half of the word at each address. We label the array address input, and connect it to both devices. Since both devices will need to be selected whenever the array is selected, we also make those connections. We connect the read/not-write signal to both devices. The 16-bit input data must be split between the two devices. We choose to use the bottom device to store the less significant byte, and the upper device to store the most significant byte. How we choose to split the data is arbitrary, as long as 8 bits go to each memory. However, when a choice is arbitrary, we should always make the simplest, most obvious choice. The output data must be connected in the same order as the input data, so that an address refers to the same location whether we are reading or writing. The net result is that each device will store half of each word, and we have in fact created a 64k x 16 memory system.
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5. Increasing Depth: 128k × 8 Array
The available 64k × 8 SRAM devices are wide enough, but they are not deep enough
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Suppose instead we want to create a memory system that is 8 bits wide, but with 128k locations. In this case, our devices are wide enough, but each has only half the required depth. We again begin by creating the memory system wrapper. Note that the data inputs and outputs are 8 bits wide, but the memory system has 17 address lines since it must address 128k locations. The required capacity is twice our device’s capacity, so two devices are required. Since the memory width is the same as the device width, we directly connect the input and output data. The read/not-write signal is again directly connected to both devices. The array has 17 address lines, A16 through A0, but each device has only sixteen address inputs. Each device will contain half of the memory’s locations, so we use one of the address lines to select the device, and the remaining address lines to index within the devices. In this case, we choose A16 to determine the device selection, and connect A15 through A0 to each devices. To have A16 choose between devices, we add a 1-to-2 decoder with enable. Since neither device should be selected when the array is not selected, we connect the array’s chip select input to the decoder’s enable input. We then connect A16 to the decoder select input. The decoder’s 0 output will be active only when the array is selected and A16 is 0, and we connect that to the lower device’s chip select input. The decoder’s 1 output will be active when the array is selected and A16 is 1, and we connect that to the upper device’s chip select input. This means that the lower device with store the 64k words whose addresses begin with 0, and the upper device will store the 64k words whose addresses begin with 1.
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6. Increasing Depth: 128k × 8 Array
The available 64k × 8 SRAM devices are wide enough, but they are not deep enough
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Let’s revisit the last problem. We start by making the same connections as last time, but this time we make a different choice with the address. We instead connect the UPPER 16 bits of the address to each device, and use the least significant bit of the address as the decoder select input. Each memory device will still store half of the array’s locations, but now the lower device will hold all locations with even addresses – in other words, with addresses that end in 0 – and the upper device will hold all locations with odd addresses – in other words, with addresses that end in 1. From a functional point of view, it really doesn’t matter which address bit we chose to select between the devices – as long as the remaining address bits go to both devices, it means that half of the words will be stored in each. In a real memory system, there may be performance issues that may make one choice better than the other, but that’s beyond the scope of our discussion.
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7. Increasing Depth: 256k × 8 Array
Array capacity now 2Mb, so requires 4 SRAM devices
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Next suppose that we want an array that has 4 times the depth of our devices. Now the array will have 18 address lines, since it contains 256k, or 2^18 locations. The array requires four devices. The input and output data is directly connected to each device; along with the read/not-write signal. From the 18-bit address, we choose to connect the 16 least significant bits to the devices. Now we must use the array’s chip select input and the 2 most significant bits of the address to select which device to enable. Because of the way we connected the address bits, each device will contain a contiguous 64k block of the total array storage. If we had chosen different address bits to select between devices, then the memory locations would have been distributed differently among those devices.
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8. Array Design Example
What if we needed to build a 128K × 16 RAM out of 64K × 8 RAMs?
The total capacity of the array is 128k × 16 = 2 Mbit
Each 64K x 8 RAM has a capacity of 64k × 8 = 512 kbit
The array will require 2 Mbit / 512 kbit = 4 devices
Now let’s consider another example. Suppose we want an array that is both deeper and wider. The array capacity is 2 megabit, but each device has a capacity of 512 kilobits. So, we will need 4 devices to construct the array.

9. Example: 128k × 16 Array 64k x 16 64k x 16 DI[15:0] DO[15:0] A[16:0]
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We start with the array wrapper, and label the internal signals. Note that the array has 17 address lines, and 16 data input/output lines. We place the four SRAM devices, based on our previous calculation. Now we can partition the problem by creating sub-arrays of the devices. We’ll start by creating two 64k x 16 sub-arrays. We create the top sub-array by connecting the lower 16 address bits to both devices. Then, we connect the upper half of the data to the left device, and the lower half of the data to the right device. We connect both devices to the read/not-write signal, and connect their chip-select signals together, resulting in a 64k by 16 memory structure. We can make the same connections on the lower two devices, except their chip-selects will be connected to a different signal compared to the top sub-array. To choose between the two sub-arrays, we use a decoder connected to the array chip select and to the most significant bit of the address. The decoder outputs are used to select between the two sub-arrays. The resulting memory array has 128k locations, each storing a 16-bit word.
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10. Example: 128k × 16 Array 128k x 8 128k x 8 DI[15:0] DO[15:0] A[16:0]
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Let’s revisit the same design problem, but this time we’ll approach it differently. We again start with the array wrapper and the four devices. But this time we’ll partition the problem by first creating two 128k x 8 sub-arrays. We create the right sub-array by connecting those devices to the least-significant 8 bits of the array data. If we look at a 16-bit binary word, this would be the right half of the word. We connect the lower 16 bits of the address to each device, and connect the read/not-write signal. The chip select signal for each device is generated by decoding the array chip select and the most significant bit of the address. The other sub array is connected similarly, except it is connected to the most-significant 8 bits of the array data. If we look at a 16-bit binary word, this would be the left half of the word. We have in fact arrived at exactly the same circuit as we did in the first version of the array; we just took a different path. When working with arrays that are larger in both depth and width than the devices that make up the array, it is often simplest to create sub-arrays of devices, then combine the sub-arrays.
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11. SRAM Array Concepts
The array capacity cannot be greater than the total capacity of the devices in the array
Each bit of any array location is stored in one and only one physical location
A read from any array address must return the data previously written to that address
Writes must only affect the addressed location
Each bit of the output data can only be driven by one device at any time
None of array devices should be selected unless the array is selected
When designing or analyzing SRAM arrays, there are several important concepts to keep in mind. First, the array must contain enough devices to have the required total capacity. Each bit of every location in the array is stored in a single, unique location. When we read from any address, the array must return the data that we wrote to that location previously. Writes to memory must not alter the data at any location except the one being addressed. You must ensure that contention does not occur on the output data lines, by ensuring that each data line is never driven by more than one device at any time. Finally, if the array is not selected, then no device in the array should be selected. This allows us to use multiple instances of an array to create an even larger array – just like we did when we first created sub-arrays, then combined those sub-arrays.

12. ECE 352 Digital System Fundamentals
SRAM Arrays
This concludes our video on SRAM arrays.