1. A 200MHz <insert E #>pJ 6-bit Absolute-Value Detector
Name 1
Name 2

2. *Replace [] with your numbers: e.g. tp = 2ns etc.
Design Summary
A) Circuit topology, B) Circuit Style (e.g. Ripple –carry Adder + Comparator, static CMOS)
C) WHY: about Area, about Delay, other (e.g. moderate Area, fast, regular design)
Note: tp = max {All Inputs  Out}
Area (A) = X[µm] × Y[µm]
*Replace [] with your numbers: e.g. tp = 2ns etc.
Schematic
Layout size
Energy
Verfication
tp_X0→OUT = []ns
X= [], Y= []
Sch E = []pJ
Func: Y / N
tp_X5→OUT = []ns
A = []µm2
Layout E = []pJ
DRC: Y / N
tp = []ns
AR = []
LVS: Y / N
EE115C – Winter 2013

3. Critical Path Analysis
Highlight critical path
block diagram of design / crit-path delay equation
SAMPLE
EE115C – Winter 2013

4. SAMPLE Design Optimization Gate level critical path
MOS detail of gates, optimizations, and sizing strategy
0.96 P0
0.96 P1
0.96 P6
0.96
T-Gate
1.44
1.44
1.44 S7 Ci P7
0.96
SAMPLE G0 G1 G6
0.96/
0.48
3.84/
1.92
0.48
0.48
0.48
CLKB
0.48
Propagate Carry instead of Carry to reduce transistor count along Manchester chain
NMOS only pass gate as all Carry nodes are pre-charged to VDD at CLK=0
Dynamic logic in Ci inverter and G0:7 AND gates  footless Domino in Manchester chain
Generate CO and Sum to incorporate the 4X buffer in signal chain.
EE115C – Winter 2013

5. SAMPLE Functionality Check
Relevant waveforms (3 most critical input to output paths)
SAMPLE
EE115C – Winter 2013

6. Absolute-Value Detector Layout
Highlight critical path 2
INPUT BUFFER
INPUT BUFFER 3
Indicate size
FA0
FA1
FA2
FA3
Y = 38.3mm
SAMPLE
X = 33.0mm
OUTPUT
BUFFER
OUTPUT
BUFFER 1
CLOCK
CHAIN
Show layout 4
OUTPUT
BUFFER
OUTPUT
BUFFER
AR, Area
Aspect ratio:
1.16
Area:
1467mm2
FA7
FA6
FA5
FA4
(6)
Anything else
Density:
85%
INPUT BUFFER
INPUT BUFFER 5
EE115C – Winter 2013

7. Any additional slides will NOT be graded
Discussion
Three most important features of your design
(e.g. Minimum delay through transistors sizing)
(e.g. Highly regular layout design made easy to route)
(e.g. Logic optimization strategy for reduced area)
Given another chance, 3 things you would do different
(e.g. Change topology, because…)
(e.g. Optimize only last few stages to save design time)
(e.g. Nothing, I nailed it down! ;))
Any additional slides will NOT be graded
EE115C – Winter 2013