1. DASC Meeting February 21, 2008 Victor Berman, Chair
Stan Krolikoski Vice Chair
Stephen Bailey, Secretary
Karen Bartleson, Treasurer

2. DASC Procedure Update Need a level of procedure document below P&Ps
For operational procedures that effect DASC only
Do not require P&P changes or SAB approval
All actions remain within P&P rules
I propose we call this DASC Operations Manual
Two examples
DASC election process
DASC PAR approval process

3. DASC Election Process Suggested update
Following close of nominations, allow a one week period for circulation of position statements
All nominees are allowed, but not required, to circulate statements that may include their experience and positions with respect to the DASC operations.
The two week period for balloting will begin following this period.
All other rules remain unchanged.

4. DASC PAR Approval Process
Currently it is not clear how to handle suggested corrections to PARs during the DASC approval ballot period.
Should the full PAR be recirculated each time there is a minor change? This would be very time consuming.
Suggestion:
The officers will monitor minor updates to the PAR to ensure that they correct the items objected to.
The person objecting will review the change to see that it satisfies the objection and will change their vote to APPROVE if it does.
Recirculation will only be done were the is a major change to the content of the PAR. This will be decided by unanimous vote of the officers.

5. DASC Standards due for maintenance in 2008
IEEE Standard VHDL Language Reference Manual
 1076 will be going to ballot later this year.  The updated standard will include , , and Should withdraw these once 1076 goes to ballot.
(R2002) IEEE Standard VHDL Mathematical Packages
            See above
IEEE Standard VHDL Synthesis Packages
IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
            This standard has been revised with corrigenda and will be balloted later this year.
IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
            See above for 1076.
IEEE Standard for Verilog Register Transfer Level Synthesis
            This should be reaffirmed.
IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System
            This will be balloted later this year.
IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process - This should be reaffirmed.
IEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks - This should be reaffirmed.