1. IRL Solutions
File Number Here

2. Outline The Value of IRL Creating an IRL System
Bitstream Delivery
Remote Reconfiguration
Where to go for more information

3. Increasing Need for Upgradable Hardware
Field Upgrade
Advantage
Time-to-Market
Advantage
IRL Based Systems
Revenue
Fixed Chip Solution
Time
Increase time in market
Reduce cost of ownership
Opportunity for new usage-based revenue

4. Useful Life of ASIC Based Product is Decreasing
IRL Based Systems
Revenue
Fixed Chip Solution
Time
End-users driving more feature upgrades
Need protection from “evolving” standards
ASIC vendors no longer doing long life support

5. Why Field Upgradability?$$
Support Emerging and Evolving Standards
Ship product prior to completion of specifications
Ship functional subset today
Xilinx customer starts product integration earlier
Algorithm Performance Upgrades
Use the software release/revenue model
Bug fixes
Reduce or eliminate the need for Field Service Technician visits $$ $$

6. IRL Value Table

7. Agenda The Value of IRL Creating an IRL System Bitstream Delivery
Remote Reconfiguration

8. Upgradable System Markets
Infrastructure
High Volume Applications / Appliances
Big Iron
Thick
Thin
Routers
Gateways
Switches
Set Top Boxes
Serial I/O Cards
Vending Machines
Network Appliances
Multiple Processor
Proprietary OS
Microprocessor
Commercial OS
Microcontroller
OS design dependent
Reduce Service Costs
Value Added Service
Reduce Service Costs
Upgrade Revenue
Usage Revenue
Reduce Service Costs
Upgrade Revenue
Usage Revenue

9. Design Issues for IRL System
Bitstream Delivery
Domain
Board Level
Domain
Security
RTOS support
Scalability
Monitoring
Reliability •
RTOS support •
Scalability •
Device support •
PAVE

10. Components of IRL System
Internet Reconfigurable Logic provides an API (PAVE) and specifies a set of XILINX design guidelines that define how remote devices can be updated via a network in a non-proprietary manner.
There are four main components in the IRL system model. These are the
Host
Network
Target
Payload
Network 2
Host 1
Target 3

11. Design Example: Residential Gateway
Target Processor
Target FPGA(s)
Host
Payload developed in Hardware/Software Co-Design Environment 1
Payload
Processing Element
Xilinx
Any Network
PAVE 3 4
System/Peripheral Bus
Processing element receives, and validates the payload prior to FPGA re-configuration
Reconfigurable logic resides here.
Upgrade
Portal 2
Target Component

12. Target Processing Element
IRL Application
Target Reconfigurable
Logic
WRS Tornado II
Target Processing Element µP
Any Network
VxWorks
PAVE enabled VxWorks application
FLASH
Upgrade
Portal
(Maintenance Center)
Host Development
Environment
Target Component

13. For More Information irl@xilinx.com wallace.westfeldt@xilinx.com

14. Appendix: PAVE Details

15. PAVE
PLD
API
VxWorks
Embedded systems
Provides a standard interface to VxWorks-based applications for the programming of Xilinx PLDs
Processing
Element
FLASH
PAVE

16. Interface to VxWorks Processing Element VxWorks logo here VxWorks PAVE
Application Program
FLASH
Function Call
PAVE

17. PAVE Features & Support
Programmable Methods
JTAG
SelectMap
Available for C, C++ or Java applications
Design Guidelines
Application
PAVE Device API
Platform Abstraction Layer (PAL)
VxWorks RTOS
BSP for WRS VxWorks RTOS
Processing Element

18. Provide a Scalable System Solution
Processing Element
RTOS
Target Processing Element
Target Reconfigurable
Logic
Xilinx
Embedded System Bus
Target Component
Big Iron Application Model Distributed Processing
Dist. Proc
Workstation
Host
Host development tools,
Integrated Development Environment (IDE)

19. Payload System Component
The payload system component is a composite element that encapsulates the re-configurable functionality of the system.
The payload can consist of a header, bitstream, and associated dynamically linkable software module.
Header
Bitstream (for FPGA)
Dynamically Loadable
Software Module
(SW Device Driver for FPGA)