1. Pipelined Array Multiplier Aldec Active-HDL Design Flow
ECE 448: Lab 3
Pipelined Array Multiplier
Aldec Active-HDL Design Flow
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University 1 1 1

2. Agenda for today Part 1: Introduction to Experiment 3:
Pipelined Array Multiplier
Part 2: Hands-on Session:
FPGA Design Flow Based on
Aldec Active HDL 2

3. Introduction to Experiment 3 Pipelined kxk-bit Array Multiplier
Part 1
Introduction to Experiment 3
Pipelined kxk-bit Array Multiplier 3

4. Notation
a Multiplicand ak-1ak a1 a0
x Multiplier xk-1xk x1 x0
p Product (a  x) p2k-1p2k p2 p1 p0

5. Multiplication of two 4-bit unsigned binary numbers in dot notation

6. Basic Multiplication Equations
k-1
x =  xi  2i
p = a  x
i=0
k-1
p = a  x =  a  xi  2i =
= x0a20 + x1a21 + x2a22 + … + xk-1a2k-1
i=0

7. Unsigned Multiplication
a4 a3 a2 a1 a0 x
x4 x3 x2 x1 x0
ax0 20
a4x0 a3x0 a2x0 a1x0 a0x0
ax1 21
a4x1 a3x1 a2x1 a1x1 a0x1 +
ax2 22
a4x2 a3x2 a2x2 a1x2 a0x2
ax3 23
a4x3 a3x3 a2x3 a1x3 a0x3
ax4 24
a4x4 a3x4 a2x4 a1x4 a0x4 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0

8. 5 x 5 Array Multiplier

9. Array Multiplier - Basic Cell
cin x y FA
cout s

10. Full-adder x cout FA y s cin x y cin cout s 1 1 1 1 11 1 1 1 1
x + y + cin = ( cout s )2

11. Typical Application of Full Adders

12. 5 x 5 Array Multiplier
with modified cells

13. Array Multiplier – Modified Basic Cellam ci
si-1 xn FA
ci+1 si

14. Pipelined 5 x 5 Multiplier
D flip-flop

15. Array Multiplier – Basic Cell 1am ci
si-1 xn FA
ci+1 si

16. Array Multiplier - Basic Cell 2x y
cin FA
cout s

17. Operation of a circuit with 4 pipeline stages
clock
cycle 1 2 3 4 5 6 7 8 S1 S2 S3 S4 S5 S6 S7 S8 S1 S2 S3 S4 S5 S6 S7 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5
clock
cycle 9 10 11 12 13 14 15 16 S9
S10
S11
S12 S8 S9
S10
S11
S12 S7 S8 S9
S10
S11
S12 S6 S7 S8 S9
S10
S11
S12

18. rising edge rising edge
Timing parameters
definition
units
pipelining
delay
time pointpoint ns
latency
time inputoutput ns
bad
#output bits/time unit
#operations/time unit
Mbits/s muls/s
throughput
good
rising edge rising edge
of clock ns
good
clock period 1
MHz
clock frequency
good
clock period

19. Xilinx CLB Slice
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

20. Xilinx Multipurpose LUT
= 16 x 1 ROM
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

21. SLR16: MLUT configured as a Shift Register
Each LUT can be configured as a shift register
Serial in, serial out
Dynamically addressable delay up to 16 cycles
For programmable pipeline
Cascade for greater cycle delays
Use CLB flip-flops to add depth D Q CE
LUT IN
CLK
DEPTH[3:0]
OUT =
The LUT can be configured as a shift register (serial in, serial out) with bit width programmable from 1 to 16. For example, DEPTH[3:0] = 0010(binary) means that the shift register is 3-bit wide. In the simplest case, a 16 bit shift register can be implemented in a LUT, eliminating the need for 16 flip flops, and also eliminating extra routing resources that would have been lowered the performance otherwise.

22. FPGA Design Flow Based on Aldec Active HDL
Part 2
Hands-on Session
FPGA Design Flow Based on Aldec Active HDL 22