1. Acceleration
How to improve speed?
At what costs?

2. T=Nq * CPI * Cycletime Nq, Number of instructions
CPI, Cycles Per Instruction
Cycletime

3. Single Cycle Design
CPI = 1
Cycletime = Long (Longest path)

4. Multiple Cycle
1 < CPI < S
Cycletime = Factor 1/S

5. Pipelined design
CPI = 1, (Constant)
Cycletime = Factor 1/S

6. “THROUGHPUT”
The total amount of work done in a given time

7. INSTRUCTION MEMORY STAGE (IM)
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
INSTRUCTION
MEMORY

8. INSTRUCTION DECODE STAGE (DE)
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend

9. INSTRUCTION EXECUTE STAGE (EX)
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend

10. DATA MEMORY STAGE (DM) DATA MEMORY Zero ext. Branch logic A ALU 4 B +A
ALU 4 B + 31 +
Sgn/Ze
extend
DATA MEMORY

11. WRITEBACK STAGE (WB) Zero ext. Branch logic A ALU 4 B + 31 + Sgn/ZeA
ALU 4 B + 31 +
Sgn/Ze
extend

12. Pipeline 5 stages, (IM, DE, EX, DM, WB) Writeback NOT in critical path
Cut critical path by 4

13. WRITEBACK STAGE (WB) Zero ext. CAN READ/WRITE THE SAME REG! Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend

14. Single Cycle IM
Reg DM
Reg IM
Reg DM
Reg

15. Single Cycle IM
Reg DM
Reg IM
Reg DM
Reg

16. 4 Stage Pipe IM
Reg DM
Reg IM
Reg DM
Reg IM
Reg DM
Reg IM
Reg DM
Reg

17. A Program 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCD
0x3C sw $5 4($0)
$1 holds value 0x05

18. 4 Stage Pipe 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCDIM
Reg DM
Reg
0x34 add $7 $0 $1 IM
Reg DM
Reg
0x38 ori $2 $0 0xABCD IM
Reg DM
Reg
0x3C sw $5 4($0) IM
Reg DM
Reg

19. Step 1 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCDIM
Reg DM
Reg
0x34 add $7 $0 $1 IM
Reg DM
Reg
0x38 ori $2 $0 0xABCD IM
Reg DM
Reg
0x3C sw $5 4($0) IM
Reg DM
Reg

20. Step 2 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCDIM
Reg DM
Reg
0x34 add $7 $0 $1 IM
Reg DM
Reg
0x38 ori $2 $0 0xABCD IM
Reg DM
Reg
0x3C sw $5 4($0) IM
Reg DM
Reg

21. Step 3 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCDIM
Reg DM
Reg
0x34 add $7 $0 $1 IM
Reg DM
Reg
0x38 ori $2 $0 0xABCD IM
Reg DM
Reg
0x3C sw $5 4($0) IM
Reg DM
Reg

22. Step 4 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCDIM
Reg DM
Reg
0x34 add $7 $0 $1 IM
Reg DM
Reg
0x38 ori $2 $0 0xABCD IM
Reg DM
Reg
0x3C sw $5 4($0) IM
Reg DM
Reg

23. Step 5 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCDIM
Reg DM
Reg
0x34 add $7 $0 $1 IM
Reg DM
Reg
0x38 ori $2 $0 0xABCD IM
Reg DM
Reg
0x3C sw $5 4($0) IM
Reg DM
Reg

24. > 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCD
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
> 0x30 sub $6 $0 $1
0x34 add $7 $0 $1
0x38 ori $2 $0 0xABCD
0x3C sw $5 4($0)

25. 0x30 sub $6 $0 $1 > 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCD
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
0x30 sub $6 $0 $1
> 0x34 add $7 $0 $1
0x38 ori $2 $0 0xABCD
0x3C sw $5 4($0)

26. 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 > 0x38 ori $2 $0 0xABCD
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
0x30 sub $6 $0 $1
0x34 add $7 $0 $1
> 0x38 ori $2 $0 0xABCD
0x3C sw $5 4($0)

27. 0x30 sub $6 $0 $1 0x34 add $7 $0 $1 0x38 ori $2 $0 0xABCD
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
0x30 sub $6 $0 $1
0x34 add $7 $0 $1
0x38 ori $2 $0 0xABCD
> 0x3C sw $5 4($0)