1. 95-1 Under-Graduate Project Fixed-point Analysis
Speaker: 陳柏偉 許名宏
Advise: Prof. An-Yeu Wu
Mentor: 陳彥良
Date: 2006/12/13
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2. Outline Major Idea of Quantization Upper Bounds Analysis
Wordlength Simulation
Design Guideline
Efficient Hardware Design
RTL of 64-Points Single-Path Delay Feedback FFT
Conclusion
Future work
Reference
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3. Major Idea of Quantization
Suppose we fixed fractional part to N bits.
Input = data we want to fix.
output = fixed Input.
Output = 0;
if input >= 2^(N-1)
input = input-2^(N-1);
output = output+2^(N-1);
N = N-1;
else
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4. Analysis Before Simulation
SQNR : Signal-to-Quantization-Noise-Ratio.
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5. Wordlength Range II=3 IF=7~10 OI=9 OF=7~10 W=6~13 integer fractional
input
II=3
IF=7~10
output
OI=9
OF=7~10
twiddle
W=6~13
Input part :10~14.
Output part : 16~20.
Twiddle factor : 6~13.
Adder (BFI,BFII) : a bit more than its input.
Multiplier : the same as output .
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6. Finding Upper Bounds (1/2)
Input power :
Noise power :
For ideal output and twiddle factor,
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7. Finding Upper Bounds (2/2)
Twiddle factor :
We can also get
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8. We expect SQNR to raise 6dB when one more bit was added.
Upper Bound Result
IF(W=100,OF=100)
W(IF=100,OF=100)
OF(IF=100,W=100) 7 8 9 10
72.14 11
86.617
We expect SQNR to raise 6dB when one more bit was added.
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9. Wordlength Simulation(1/3)
Fixed number of bits in fractional part of input data : 10
Twiddle factor : 6~13
Fractional part of output data : 7~11
SQNR (dB)
Output fractional bits
Twiddle factor bits
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10. Wordlength Simulation(2/3)
SQNR (dB)
Fixed number of bits in twiddle factor : 11
Fractional part of input data : 7~11
Fractional part of output data : 7~11
input fractional bits
Output fractional bits
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11. Wordlength Simulation(3/3)
Fixed number of bits in fractional part of output data : 10
Twiddle factor : 6~13
Fractional part of input data : 7~11
SQNR (dB)
Twiddle factor bits
input fractional bits
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12. Hardware Cost V.S. Accuracy(1/2)
Fix W= 11 & OF=8 or 9 , plot relations between IF bits & SQNR.
Starts to saturate
Starts to saturate
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13. Hardware Cost V.S. Accuracy(2/2)
Fix OF= 8 & IF=7 or 8 , plot relations between W bits & SQNR. .
Starts to saturate
Starts to saturate
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14. Design Guideline
Concluding from the former simulations ,we can discover:
When W is 2 bits higher than IF, then SQNR arise little when adding bits to W; when IF is 1~2 bit(s) higher than OF, then SQNR arise little when adding bits to IF.
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15. Efficient Hardware Design
We want to use least resources to achieve acceptable performance. While trading off between accuracy and speed (resources), we found under
IF=> 8 bits, W=>10 bits, OF=>7 bits,
SQNR ~ 54 dB
we can receive what we want (SQNR>50dB).
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16. RTL of 64-Points Single-Path Delay Feedback FFT
input
output
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17. Confirming Results
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18. Conclusion SQNR arise 6dB when one more bit is added.
Knowing whether it’s worth adding one more bit to improve accuracy without actual simulation.
An efficient design which meets the condition SQNR > 50dB would be
IF=> 8 bits, W=>10 bits, OF=>7 bits.
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19. Future work Flexible bits (64, 128, and 256-points)
RTL design improvement : timing & area
Memory reduction of twiddle factor
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20. Reference
[1] Discrete-time signal process 2nd edition A.V. Oppenheim R.W Schafer. Prentice Hall ,February 15, 1999.
[2]D. Menard, R. Rocher, P. Scalart and O. Sentieys. “Automatic SQNR Determination in Non-Linear and Non-Recursive Fixed-Point System.”
Matlab:
SQNR:
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