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332:437 Lecture 9 Verilog Example

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Presentation on theme: "332:437 Lecture 9 Verilog Example"— Presentation transcript:

1 332:437 Lecture 9 Verilog Example
Verilog Design Methodology Pinball Machine Verilog Coding States State transition diagram Final Verilog Code Summary 4/30/2019 Bushnell: Digital Systems Design Lecture 9

2 Verilog Design Methodology
Draw a System Block Diagram As if you were designing the hardware by hand Label all signals For each block: Determine whether it is controlled by clocks or reset signals If so, it is sequential If not, it is combinational 4/30/2019 Bushnell: Digital Systems Design Lecture 9

3 Verilog Design Methodology
Combinational blocks Map into combinational always block or into assign statement Sequential blocks Map into always block controlled by: {posedge, negedge} clk {posedge, negedge} reset, set 4/30/2019 Bushnell: Digital Systems Design Lecture 9

4 Verilog Design Methodology
Add an initial block for the testbench Add additional always block to generate the clock Add additional sequential always blocks for every counter 4/30/2019 Bushnell: Digital Systems Design Lecture 9

5 Example -- Design a Pinball Machine
After left-flipper or right-flipper pressed If ball in 100 point slot, pt (green) If ball in 200 point slot, pt (yellow) If point hits in a row, enable big_bopper slot (red) If big_bopper slot enabled and hit (gold), Get 600 points Increment free_game count If ball_lost, go back to start state 4/30/2019 Bushnell: Digital Systems Design Lecture 9

6 Hardware Visualization
100 200 bop_hit green yellow red Gold bop_en Next State Decoder Output Clock Generator State Register Point Counter Game Testbench pgames ppoints 4/30/2019 Bushnell: Digital Systems Design Lecture 9

7 State Transition Diagram
Need these states: init – initialize the machine start – waiting for input h200one – hit 200 point hole once h200two – hit 200 point hole twice h200three – hit 200 point hole 3 X 4/30/2019 Bushnell: Digital Systems Design Lecture 9

8 Bushnell: Digital Systems Design Lecture 9
Verilog Coding Write an always block for each box on the prior slide One exception – combine next state and output decoders into 1 always block Why? For clarity Less code to write Guaranteed that both decoders activate under same conditions 4/30/2019 Bushnell: Digital Systems Design Lecture 9

9 State Transition Diagram
ball_lost neither ball_lost neither init start h200one h200 h100 h100 h100 ball_lost h200 h100 ball_lost h200two h200 h200three neither bop_hit h200 neither 4/30/2019 Bushnell: Digital Systems Design Lecture 9

10 Evolution of Verilog Code
Combined next state and output decoders into one always block for clarity design_analyzer objected to clock generator process – moved it to the testbench Forgot to code hardware for bop_enable – fixed that vcs objected to sensitivity list of clock generator – combined it with rest of testbench Corrected testbench and it worked! 4/30/2019 Bushnell: Digital Systems Design Lecture 9

11 Bushnell: Digital Systems Design Lecture 9
Module Declaration module pinballmachine (input clk, reset_bar, output reg [0:2] pstate, output reg [0:2] nstate, output reg [0:4] games, output reg [0:15] points, output reg [0:4] pgames, output reg [0:15] ppoints, input h100, h200, bop_hit, ball_lost, output reg bop_en, green, yellow, red, gold); 4/30/2019 Bushnell: Digital Systems Design Lecture 9

12 Bushnell: Digital Systems Design Lecture 9
Declaration of states parameter init = 0, start = 1, h200one = 2, h200two = 3, h200three = 4; 4/30/2019 Bushnell: Digital Systems Design Lecture 9

13 Bushnell: Digital Systems Design Lecture 9
State Flip-flops // State flipflops clk, negedge reset_bar) begin if (reset_bar == 0) pstate <= init; else pstate <= nstate; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

14 Next State/Output Decoder
// Next state and output decoder begin case (pstate) init: begin nstate <= start; points <= 0; games <= 0; green <= 0; yellow <= 0; red <= 0; gold <= 0; bop_en <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

15 Next State/Output Decoder
start:begin bop_en <= 0; if (! ball_lost) begin if (h100 == 1) begin nstate <= start; points <= ppoints + 100; games <= 0; green <= 1; yellow <= 0; red <= 0; gold <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

16 Next State/Output Decoder
else if (h200 == 1) begin nstate <= h200one; points <= ppoints + 200; games <= 0; green <= 0; yellow <= 1; red <= 0; gold <= 0; end else begin nstate <= start; points <= 0; games <= 0; end end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

17 Next State/Output Decoder
else begin nstate <= start; points <= 0; games <= 0; green <= 0; yellow <= 0; red <= 0; gold <= 0; end end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

18 Next State/Output Decoder
h200one: begin bop_en <= 0; if (! ball_lost) begin if (h100 == 1) begin nstate <= start; points <= ppoints + 100; games <= 0; green <= 1; yellow <= 0; red <= 0; gold <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

19 Next State/Output Decoder
else if (h200 == 1) begin nstate <= h200two; points <= ppoints + 200; games <= 0; green <= 0; yellow <= 1; red <= 0; gold <= 0; end else begin nstate <= h200one; points <= 0; games <= 0; end end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

20 Next State/Output Decoder
else begin nstate <= start; points <= 0; games <= 0; green <= 0; yellow <= 0; red <= 0; gold <= 0; end end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

21 Next State/Output Decoder
h200two: begin if (! ball_lost) begin if (h100 == 1) begin nstate <= start; points <= ppoints + 100; games <= 0; green <= 1; yellow <= 0; red <= 0; gold <= 0; bop_en <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

22 Next State/Output Decoder
else if (h200 == 1) begin nstate <= h200three; points <= ppoints + 200; games <= 0; green <= 0; yellow <= 0; red <= 1; gold <= 0; bop_en <= 1; end else begin nstate <= h200two; points <= 0; games <= 0; end end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

23 Next State/Output Decoder
else begin nstate <= start; points <= 0; games <= 0; green <= 0; yellow <= 0; red <= 0; gold <= 0; bop_en <= 0; end end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

24 Next State/Output Decoder
h200three: begin if (! ball_lost) begin if (h100 == 1) begin nstate <= start; points <= ppoints + 100; games <= 0; green <= 1; yellow <= 0; red <= 0; gold <= 0; bop_en <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

25 Next State/Output Decoder
else if (h200 == 1) begin nstate <= start; points <= ppoints + 200; games <= 0; green <= 0; yellow <= 1; red <= 0; gold <= 0; bop_en <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

26 Next State/Output Decoder
else if (bop_hit == 1) begin nstate <= start; points <= ppoints + 600; games <= pgames + 1; green <= 0; yellow <= 0; red <= 0; gold <= 1; bop_en <= 0; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

27 Next State/Output Decoder
else begin nstate <= h200three; points <= 0; games <= 0; end end else begin nstate <= start; points <= 0; games <= 0; green <= 0; yellow <= 0; red <= 0; gold <= 0; bop_en <= 0; end end endcase end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

28 Bushnell: Digital Systems Design Lecture 9
Point Counter // Point counter clk, negedge reset_bar) begin if (reset_bar == 0) ppoints <= 0; else if (points) ppoints <= points; end 4/30/2019 Bushnell: Digital Systems Design Lecture 9

29 Bushnell: Digital Systems Design Lecture 9
Game Counter // Game counter clk, negedge reset_bar) begin if (reset_bar == 0) pgames <= 0; else if (games) pgames <= games; end endmodule 4/30/2019 Bushnell: Digital Systems Design Lecture 9

30 Bushnell: Digital Systems Design Lecture 9
system Module module system (); wire clk; wire reset_bar; wire [0:2] pstate; wire [0:2] nstate; wire [0:4] games; wire [0:15] points; wire [0:4] pgames; wire [0:15] ppoints; wire h100, h200, bop_hit, ball_lost; wire bop_en; wire green, yellow, red, gold; pinballmachine (clk, reset_bar, pstate, nstate, games, points, pgames, ppoints, h100, h200, bop_hit, ball_lost, bop_en, green, yellow, red, gold); testbench (clk, reset_bar, pstate, nstate, games, points, pgames, ppoints, h100, h200, bop_hit, ball_lost, bop_en, green, yellow, red, gold); endmodule 4/30/2019 Bushnell: Digital Systems Design Lecture 9

31 Bushnell: Digital Systems Design Lecture 9
Summary Still need to visualize the hardware as combinational and sequential blocks in block diagram when using Verilog Still need to design tight state transition diagram Blocks in diagram translate into always/assign statements 4/30/2019 Bushnell: Digital Systems Design Lecture 9

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