1. Global chip connections
I2C High speed :
up to 3.4Mb/s
VDD 1.2V
GND 0V
JTAG/
I2C
serial DCS transceiver:
bias, thresholds, masks, etc.
Column logic
pixel array
Settings data
BCR
ECR
Clock
Trigger
Clock & trigger
receiver
40MHz clock
trigger
trigger BX number
Serial Data Out, 1Gb/s (copper)
add event & Bunch ID
physical data:
with 8-10 bit
coding 1.2Gb/s
fixed latency (programmable in chip)
clock 40MHz
4/24/2019

2. Chip level readout 4/24/2019 token, to all columns trigger 256 columns
readout control
clock
trigger
BCR
ECR
16 bits readout bus
16 bits readout bus
16 bits readout bus
trigger
Trigger EID fifo
“TTCRX”
clock
8b trigger latency
clock
256 cells per column
BID counter 11 bits
distribute 8 bits trigger latency,
clock, trigger and token.
24 bits readout bus
event counter
token return= ready with event readout
what if the buffer is full ?? T
column buffer
token from column to column T
column buffer T
column buffer
add col nr.
add event ID & BID
FIFO
24b par => ser 1Gb/s
write_busy2
also add start- and end of event.
Skip column if empty
pixel to column hand-shake with write-busy1
column buffer to link FIFO hand-shake with write-busy2
until previous column ready
@Token the pixel cell copies its triggered data in the column buffer.
Readout starts automatic after token comes out of first column.
Asynchronous process, speed determined by serial data link (busy as handshake)
This means the pixel cell and column buffer readout faster then 40MHz.
4/24/2019

3. Pixel cell functionality
Digital approach
additional signals:
reset
test pulse
clear buffers ?
Implemented in GOSSIPO02 Nov. 2006
Token
8 bit BunchCrossingID
16 bits readout bus
threshold
DAC,4b
tune
Trigger fixed latency)
hit-low
measure & readout control logic
start
560 MHz osc.
pad
hit flag (trigger FIFO)
hit-high
@token
2 hits buffer
count
pre-load
==1?
DAC,4b
select
4b counter
4b counter
latency counter
4b counter
4b counter
latency counter
row
mask& test
Clear buffer
==0? +
write data
Time Measurement & hit hold:
@hit_low count1 560MHz & start latency counter
@hit_high count2 560MHz
@ BunchClk stop 560MHz (count1 & count2)
if (latency=0) clear buffer flag.
hit-low & hit High 1.56ns res., max 25ns.
write_busy
if counter = 0 : free buffer location
Trigger and Readout:
@ trigger : write hitFlag in trigger FIFO & start Lat. counter
@ token: if (write_busy) hold Token if (hitFLAG) write value to bus and clear buffer location
pass token to next pixel cell
step 1 within 25ns
step 2 to 3 to next pixel with data within 25ns.
DCS:
per pixel:
DAC 4bit
Mask & test 2bit
osc tune 4b
chip level:
bias DAC’s 8* 8bit
total data:64k + 64b.
Token to next pixel
Serial control bus.
8 bias lines.
Average total readout time : 5.8us
trigger L1 latency : 2.5us
pixel dead time : max 400ns
write_busy
4/24/2019

4. Pixel cell functionality
Digital approach
8 bits trigger latency
trigger
token
16 bits readout bus
test mask, 2b
40MHz
write_busy
preamp & shaper & discriminator
start/stop fast/slow
HIT
start
if hitFlag & no write_busy: write to bus
clear
16 bits differential bus driver
threshold DAC 8b
trigger FIFO
load
clear
Buffer 0
full flag
4b LE counter
4b TE counter
latency count
=0?
=1?
hitFlag
hitFlag
hitFlag
hitFlag
load
clear
Buffer 1
full flag
4b LE counter
4b TE counter
latency count
=0?
=1?
hitFlag
hitFlag
hitFlag
hitFlag
@ trigger write “=1?” result in trigger FIFO.
@ token check if HitFlag is set, and
if so, write corresponding data to readout bus
560MHz clock
or 560MHz
+8bits row nr.
The choice of 1 ore 2 thresholds does
make a big difference in the principle of
measurement and data handling in the pixel cell. Therefore the original (1 thr.) is kept here.
4/24/2019

5. IC Technology (130nm) layer cross section
Technology option :
8 Metal layers; 6 thin 2 thick
DV-Wire bond Pad
polyimide TD
nitride
Oxide TV LM
Power : Vdd VQ
bus routing MQ VL M6
Power & shield : GND V5
bus routing M5 V4
bus routing M4 V3 M3
Power & shield : GND V2
PC, M1 & M2 : circuit routing M2 V1 M1
Salicide CA PC PC RX RX
N-WELL RX RX
4/24/2019