1. Lecture 34 Syed Mansoor Sarwar
Operating Systems
Lecture 34
Syed Mansoor Sarwar

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Agenda for Today
Review of previous lecture
Protection in paging
Structure of the page table
Multi-level paging
Hashed page tables
Inverted page table
Sharing in paging
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Review of Lecture 33
Addressing and logical to physical address translation
Examples: Intel P4 and PDP-11
Page table implementation
Performance of paging
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Example
Tmem = 100 nsec
TTLB = 20 nsec
Hit ratio is 98%
Teffective = ?
Teffective = 0.98 ( )
(20 + 2x100)
= 122 nanoseconds
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Protection
Memory protection in paging is achieved by associating protection bit with each page table entry
Valid/Invalid bit (v)—page in the process address space or not
Read, write, and execute bits (r, w, x)
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Protection
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7. Structure of the Page Table
Hierarchical / Multilevel Paging
Hashed Page Table
Inverted Page Table
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Multilevel Paging
Logical address = 32-bit
Page size = 4K bytes (212 bytes)
Page table entry = 4 bytes
Maximum pages in a process address space = 232 / 4K = 1M
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Multilevel Paging
Maximum pages in a process address space = 232 / 4K = 1M
Page table size = 4M bytes
This page cannot fit in one page  Page the page table
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Multilevel Paging
Page table needed for keeping track of pages of the page table—called the outer page table or page directory
No. of pages in the page table is 4M / 4K = 1K
Size of the outer page table is 1K * 4 bytes = 4K bytes  outer page will fit in one page
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Multilevel Paging
2-level paging
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Multilevel Paging
Addressing and address translation
32-bit logical address: p1 used to index the outer page table and p2 to index the inner page table
page number
page offset p1 p2 d 10 10 12
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Multilevel Paging
p1{
p2{
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Multilevel Paging
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DEC VAX
Logical address = 32 bits
Page size = 512 bytes = 29 bytes
Process address space divided into four equal sections
Pages per section = 230 / = 221 = 2M
Size of a page table entry = 4 bytes
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DEC VAX
Bits needed for page offset = log2 512 = 9 bits
Bits to specify a section = log = 2 bits
Bits needed to index page table for a section = log2 221 = 21 bits
Size of a page table = 221 * = 8 MB
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DEC VAX
8 MB page table is paged into 8MB / 512 = 2 K pages
Size of the outer page table (2K * 4 = 8 KB) is further paged, resulting in 3-level paging per section
section
page number
page offset p s d
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More Examples
32-bit Sun SPARC supports level paging
32-bit Motorola supports 4-level paging
64-bit Sun UltraSPARC supports 7-level paging – too many memory references needed for address translation
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Hashed Page Table
A common approach to handle address spaces larger then 32 bits
Usually open hashing is used
Each entry in the linked list has three fields: page number, frame number for the page, and pointer to the next element—(p, f, next)
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Hashed Page Table
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Inverted Page Table
One entry per real page in memory
Page table size is limited by the number of frames (i.e., the physical memory) and not process address space
Each entry in the page table contains (pid, p)
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Inverted Page Table
If a page ‘p’ for a process is loaded in frame ‘f’, its entry is stored at index ‘f’ in the page table
We effectively index the page table with frame number; hence the name inverted page table
Examples: 64-bit UltraSPARC and PowerPC
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Inverted Page Table
Frame Number
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Recap of Lecture
Structure of the page table
Multi-level paging
Hashed page tables
Inverted page table
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Operating Systems
Lecture 34
Syed Mansoor Sarwar
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