1. Alan Mishchenko Department of EECS UC Berkeley
Task ID: Deep Integration of Computation Engines for Scalability in Synthesis and Verification
Alan Mishchenko
Department of EECS
UC Berkeley

2. Task Overview SRC task ID: 2867.001 Start date: 1-Jan-2019
Thrust area: CADT
Task leaders:
Alan Mishchenko, Univ. of California/Berkeley
Industrial liaisons:
See next slide
Students:
Cameron Rasmussen (graduating spring 2019)

3. Industrial Liaisons IBM Intel Mentor (Siemens) Texas Instruments
Jason Baumgartner
Victor Kravets
Intel
Timothy Kam
Michael Kishinevsky
Mentor (Siemens)
Pankaj Chauhan
Texas Instruments
Devanathan Varadarajan
Venkatraman Ramakrishnan

4. Active Collaborators Discuss, publish, exchange visits with:
EPFL, Switzerland (group of Professor G. De Micheli)
Tokyo University, Japan (group of Professor M. Fujita)
Ritsumeikan University, Kyoto, Japan (group of Professor S. Yamashita)
UFRGS, Brazil (group of Professor A. Reis)
NTU, Taiwan (group of Professor R. Jiang)
CCU, Taiwan (group of Professor M. Lin)
Fudan University, China (group of Professor L. Wang)
UMass, Amherst (group of Professor M. Ciesielski)
HKUST, Hong Kong (group of Professor K.-T. Cheng)

5. Anticipated Results
This proposal addresses the need for improved SAT sweeping, the key computation used in logic synthesis and formal verification.
Upon completion of the project, a number of hard computations in a typical EDA flow will get a performance boost.

6. Responding to the Needs of SRC Companies
Impact on logic synthesis
S3 System Tools
S3.3 Advanced logic/physical/high-level synthesis and cross-boundary optimization.
Impact on formal verification
V1 Verification Core Technologies
V1.2 Advances in techniques to boost the scalability of core verification of ML-oriented and secure hardware, both for falsification and proofs.

7. Task Deliverables Year 1
First release of the software framework for deeper integration of simulation and Boolean satisfiability. Evaluation on public benchmarks (Software, Report) [06/30/19]
Tuning of the software framework for better scalability and runtime. Evaluation on industrial problems (Software, Report) [12/31/19]
Year 2
Software release of the improved circuit-based solver. Evaluation on industrial problems (Software, Report) [12/31/20]
Year 3
Software release of the framework integrated with a number of application packages. Evaluation on industrial problems (Software, Report) [12/31/21]

8. Background and Motivation
Efficient functional representation is key for EDA tools.
In the last two decades, compact And-Inverter Graphs (AIGs), bit-parallel simulation (SIM), and Boolean satisfiability (SAT) replaced BDDs in many applications.
As a result, state-of-the-art EDA tools represent circuits using AIGs and rely on SIM+SAT for manipulation.
The scalability of these applications is limited because
(1) off-the-shelf award-winning SAT solvers do not perform well in EDA applications, which often require solving a large number of relatively easy incremental subproblems;
(2) deriving CNF from the circuit often dominates the runtime of EDA applications based on the CNF-based solver,
(3) there is a disconnect between SAT generating CEXes, one at a time, and SIM re-simulating CEXes in batches.
This work addresses these limitations by deeply integrating SIM and SAT on top of a new AIG package.

9. Summary of Recent Progress for Each Technical Goal
1st year: The initial software framework for deeper integration of simulation and Boolean satisfiability
We developed a prototype of a bit-parallel simulation engine and a circuit-based SAT solver integrated on top of a new AIG package, as discussed in the project description. Initial experimental results are encouraging: speed-ups of 2-5x in SAT sweeping are obtained.
Improvement to the circuit-based solver are currently under way.
Integration with application packages is part of future work.
2nd year: An improved circuit-based solver
3rd year: Integration of the framework into a number of application packages in synthesis and verification

10. Comparison with Existing Work
Improved circuit-based solving compared to
F. Lu, L.-C. Wang, K.-T. Cheng, R. C.-Y. Huang, “A circuit SAT solver with signal correlation guided learning”. Proc. DATE ‘03.
Improved SAT sweeping compared to
A. Kuehlmann, “Dynamic transition relation simplification for bounded property checking”. Proc. ICCAD ’04.
Improved framework based on deeper integration of simulation and SAT compared to
A. Mishchenko, S. Chatterjee, R. Jiang, and R. K. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification". ERL Technical Report, EECS Dept., UC Berkeley, March 2005. 10

11. Research Overview AIG, SIM, SAT Traditional use of SIM and SAT
Motivation for a deeper integration
Additional book-keeping
Window-based computing
Local fanout for nodes in the window
Modified SAT takes advantage of the local fanout
Modified SIM takes advantage of the local fanout
Experiments 11

12. And-Inverter Graph (AIG)
AIG is a Boolean network composed of two-input ANDs and inverters.
cdab 00 01 11 10 1
F(a,b,c,d) = ab + d(ac’+bc) b c a d
6 nodes
4 levels
F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d)
cdab 00 01 11 10 1 a c b d
7 nodes
3 levels

13. Simulation (SIM)
Assigns particular (or random) values at the primary inputs
Multiple simulation patterns are packed into 32- or 64-bit strings
Simulates in a topological order
Works well for an AIG due to
The uniformity of AND-nodes
Speed of bitwise simulation
Topological ordering of memory reducing CPU cache misses when accessing the simulation patterns 1 2 3 4 1 a b c d 1 2 3 4 1 1 2 3 4 1 1 2 3 4 1 1 1 1

14. SAT in Practical Applications
Netlist
Answer: “SAT” or “UNSAT”
CNF
SAT solver
CNF generator
CNF
Design constraints
If SAT, a counter-example
If UNSAT, a core
User cost functions
Both counter-examples and cores are useful in SAT-based applications.
In practice, cores are often represented as subsets of assumptions that make the problem UNSAT.

15. SIM and SAT SIM is faster than SAT (P vs NP)
SIM is often used before SAT to disprove easy properties
It takes SAT longer to disprove properties not disproved by SIM
This is why, state-of-the-art engines re-simulate CEXes returned by earlier SAT calls to disprove new properties before trying SAT on them
The problem is
Re-simulating each assignment over a large AIG is very slow
But, if we do not re-simulate, SAT is very slow
Previous solution: batching
Collect and re-simulate N (for example, N=16) assignments at once
Both SIM and SAT runtime is better (but is still slow)
In this work, we propose a more efficient solution
It is based on a deeper integration of SIM and SAT

16. Case Study: SAT sweeping
SAT sweeping computes functionally equivalent nodes used in
Deleting functionally equivalent nodes during logic synthesis
Combinational / sequential synthesis and verification
Computing structural choices to improve area/delay after tech-mapping
Solving multiple safety properties for the same design
Bridging implementation and specification during functional ECO
Transferring names from the initial netlist to the final netlist
Used with modifications in
High-effort resynthesis for delay/area/power/congestion
Optimization with external and observability don’t-cares (ODCs)
Traversal-based computations comparing node functions in terms of PIs under ODCs (ATPG, redundancy removal, false path detection, etc)
Property directed reachability (PDR aka IC3)
SAT sweeping is hard for AIGs with 100+ logic levels and 1M+ nodes
Efficient use of SIM and SAT is needed
In this work, SAT sweeping is used as a case-study to illustrate a deeper integration of SIM and SAT

17. Proposed SAT Sweeping Ecosystem

18. Window-Based Computation
Our goals: scalability, fast runtime, low-memory
Considering the whole circuit is counter-productive
Instead, we consider a “moving window”
SIM and SAT work on nodes in the window
Book-keeping info is kept only for these nodes
Windowing is dynamic
When computation moves to a different location, window is updated (and book-keeping information re-computed)
Boolean network (AIG)
Target nodes
Current window
Future window
Previous window

19. Circuit-Based Solver (CBS)
Works on nodes in a window
Data structure resizes when new nodes are added to the window
Uses circuit for BCP and CNF for learned clauses
Otherwise, similar to MiniSAT / Glucose
Generates incomplete assignments
This reduces work by both SAT and SIM
Incomplete assignments are possible due to the use of “J-frontier”, a key feature of CBS

20. Local Fanout The proposed SAT solver works on the circuit
Propagating in the direction of fanins is easy
Propagating in the direction of fanouts requires having fanout info available
Using global fanout info (fanouts for all nodes) is not efficient
This is because it forces the SAT solver to propagate constraints to all fanouts, including those outside of the TFO cone of the target node(s)
This is why we maintain local fanout info
Only for the nodes in the window (excluding side nodes and their fanouts)
Local fanout is kept in a dedicated manager and dynamically updated
Boolean network (AIG)
Target node whose value is computed by the SAT solver
Useless fanouts
Useful fanouts
Current window
Node looked at by the solver

21. Deeper Integration of SIM and SAT
Recall that previous work resorts to batching
Collects and re-simulates N (for example, N=16) assignments at once
Both SIM and SAT take less time (but still slow)
In this work, we propose a better solution
The idea is to perform eager re-simulation (no batching) of CEXes while relying on deeper integration of SIM and SAT
The runtime is not a problem because
Circuit-based SAT is fast and results in incomplete assignments
SIM is fast when applied to only affected nodes in the window
The cumulative runtime reduction of SAT sweeping is 2-5x

22. Experimental Results
Preliminary experiments, comparing two SAT solvers
CNF-based solver MiniSAT
Circuit-based solver CBS developed for the proposed ecosystem
The benchmarks are two AIGs derived by recording the sequence of SAT calls while processing a large design with
Sequential signal correspondence (command scorr in ABC)
Computing structural choices (command dch in ABC)

23. Experimental Results

24. Discussion CBS is faster than MiniSAT because
It does not need to generate and load CNF
Saves time because the majority of runs are easy (solved by BCP without conflicts)
It generates incomplete assignments
Less BCP to do and less work for the simulator
It uses local fanout and incremental window updating

25. Relevant Recent Publications
Deeper integration of simulation and SAT solving
- A. Mishchenko and R. Brayton, "Integrating AIG package, simulator, and SAT solver", Proc. IWLS'18.
Parallelizing logic synthesis and SAT sweeping
- V. N. Possani, Y.-S. Lu, A. Mishchenko, K. Pingali, R. Ribas, and A. Reis, "Unlocking fine-grain parallelism for AIG rewriting", Proc. ICCAD'18.
- V. N. Possani, A. Mishchenko, R. Ribas, and A. Reis, "Parallel combinational equivalence checking", Submitted to IWLS'19.
Applications of Boolean methods
- E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, Ch. Casares, P.-E. Gaillardon, and G. De Micheli, "Scalable Boolean methods in a modern synthesis flow", Proc. DATE'19.
- H. Riener, W. Haaswijk, A. Mishchenko, G. De Micheli, and M. Soeken, "On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis", Proc. DATE'19.
- H. Riener, E. Testa, W. Haaswijk, M. Soeken, L. Amaru, A. Mishchenko, and G. De Micheli, "Scalable generic logic synthesis: One approach to rule them all", DAC'19.

26. Conclusions Reviewed the SRC task (first year)
“Deep Integration of Computation Engines for Scalability in Synthesis and Verification”
Discussed ongoing and forthcoming work
Reviewed recent publications