1. Lecture 2
VHDL Refresher
ECE 448 – FPGA and ASIC Design with VHDL

2. Reading Required Recommended P. Chu, FPGA Prototyping by VHDL Examples
Chapter 1, Gate-level combinational circuit
Recommended
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design
Chapter 2.10, Introduction to VHDL
ECE 448 – FPGA and ASIC Design with VHDL

3. Recommended reading Wikipedia – The Free On-line Encyclopedia
VHDL -
Verilog -
ECE 448 – FPGA and ASIC Design with VHDL

4. Recommended reading Required for Lab 1!
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 3, RT-level combinational circuit
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design
Chapter 6, Combinational-circuit building blocks
ECE 448 – FPGA and ASIC Design with VHDL

5. Brief History of VHDL
ECE 448 – FPGA and ASIC Design with VHDL

6. VHDL
VHDL is a language for describing digital hardware used by industry worldwide
VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
ECE 448 – FPGA and ASIC Design with VHDL 8

7. Genesis of VHDL State of art circa 1980
Multiple design entry methods and
hardware description languages in use
No or limited portability of designs
between CAD tools from different vendors
Objective: shortening the time from a design concept to implementation from
18 months to 6 months
The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is the product of a US Government request for a new means of describing digital hardware. The Very High Speed Integrated Circuit (VHSIC) Program was an initiative of the Defense Department to push the state of the art in VLSI technology, and VHDL was proposed as a versatile hardware description language.
ECE 448 – FPGA and ASIC Design with VHDL 9

8. A Brief History of VHDL June 1981: Woods Hole Workshop
July 1983: contract awarded to develop VHDL
Intermetrics
IBM
Texas Instruments
August 1985: VHDL Version 7.2 released
December 1987:
VHDL became IEEE Standard and in 1988 an ANSI standard
The contract for the first VHDL implementation was awarded to the team of Intermetrics, IBM, and Texas Instruments in July However, development of the language was not a closed process and was subjected to public review throughout the process (accounting for Versions 1 through 7.1). The final version of the language, developed under government contract, was released as VHDL Version 7.2.
In March 1986, IEEE proposed a new standard VHDL to extend and modify the language to fix identified problems. In December 1987, VHDL became IEEE Standard VHDL was again modified in September 1993 to further refine the language. These refinements both clarified and enhanced the language. The major changes included much improved file handling and a more consistent syntax and resulted in VHDL Standard
ECE 448 – FPGA and ASIC Design with VHDL 10

9. Four versions of VHDL Four versions of VHDL: IEEE-1076 1987
IEEE  most commonly supported by CAD tools
IEEE (minor changes)
IEEE (minor changes)
ECE 448 – FPGA and ASIC Design with VHDL

10. Verilog
ECE 448 – FPGA and ASIC Design with VHDL

11. Verilog Essentially identical in function to VHDL
No generate statement
Simpler and syntactically different
C-like
Gateway Design Automation Co., 1985
Gateway acquired by Cadence in 1990
IEEE Standard
Early de facto standard for ASIC programming
Programming language interface to allow connection to non-Verilog code
ECE 448 – FPGA and ASIC Design with VHDL

12. VHDL vs. Verilog Government Developed Commercially Developed Ada based
C based
Strongly Type Cast
Mildly Type Cast
Case-insensitive
Case-sensitive
Difficult to learn
Easier to Learn
More Powerful
Less Powerful
ECE 448 – FPGA and ASIC Design with VHDL

13. How to learn Verilog by yourself ?

14. How to learn Verilog by yourself ?
ECE 448 – FPGA and ASIC Design with VHDL

15. Features of VHDL and Verilog
Technology/vendor independent
Portable
Reusable
ECE 448 – FPGA and ASIC Design with VHDL

16. VHDL Fundamentals
ECE 448 – FPGA and ASIC Design with VHDL

17. Naming and Labeling (1) VHDL is case insensitive Example:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent
ECE 448 – FPGA and ASIC Design with VHDL

18. Naming and Labeling (2) General rules of thumb (according to VHDL-87)
All names should start with an alphabet character (a-z or A-Z)
Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)
Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)
All names and labels in a given entity and architecture must be unique
ECE 448 – FPGA and ASIC Design with VHDL

19. Valid or invalid? 7segment_display A87372477424 Adder/Subtractor
/reset
And_or_gate
AND__OR__NOT
Kogge-Stone-Adder
Ripple&Carry_Adder
My adder
ECE 448 – FPGA and ASIC Design with VHDL

20. Free Format VHDL is a “free format” language
No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.
Example:
if (a=b) then or
if (a=b) then
if (a =
b) then
are all equivalent
ECE 448 – FPGA and ASIC Design with VHDL

21. Readability standards & coding style
Adopt readability standards based on one of the the two main textbooks:
Chu or Brown/Vranesic
Use coding style recommended in
OpenCores Coding Guidelines
linked from the course web page
Strictly enforced by the lab instructors and myself.
Penalty points may be enforced for not following
these recommendations!!!
ECE 448 – FPGA and ASIC Design with VHDL

22. Comments Comments in VHDL are indicated with
a “double dash”, i.e., “--”
Comment indicator can be placed anywhere in the line
Any text that follows in the same line is treated as
a comment
Carriage return terminates a comment
No method for commenting a block extending over a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; reading data from the input FIFO
ECE 448 – FPGA and ASIC Design with VHDL

23. Comments Explain Function of Module to Other Designers
Explanatory, Not Just Restatement of Code
Locate Close to Code Described
Put near executable code, not just in a header
ECE 448 – FPGA and ASIC Design with VHDL

24. Design Entity
ECE 448 – FPGA and ASIC Design with VHDL

25. Example: NAND Gate a b z 1 a z b1 a z b
ECE 448 – FPGA and ASIC Design with VHDL

26. Example VHDL Code 3 sections to a piece of VHDL code
File extension for a VHDL file is .vhd
Name of the file should be the same as the entity name (nand_gate.vhd) [OpenCores Coding Guidelines]
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
LIBRARY DECLARATION
ENTITY DECLARATION
ARCHITECTURE BODY
ECE 448 – FPGA and ASIC Design with VHDL

27. Design Entity Design Entity - most basic building block of a design.
entity declaration
architecture 1
architecture 2
architecture 3
design entity
Design Entity - most basic building block of a design.
One entity can have many different architectures.
ECE 448 – FPGA and ASIC Design with VHDL

28. Entity Declaration
Entity Declaration describes the interface of the component, i.e. input and output ports.
Entity name
Port type
Port names
Semicolon
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC );
END nand_gate;
No Semicolon after last port
Reserved words
Port modes (data flow directions)
ECE 448 – FPGA and ASIC Design with VHDL

29. Entity declaration – simplified syntax
ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type);
END entity_name;
ECE 448 – FPGA and ASIC Design with VHDL

30. Port Mode IN a Port signal Entity Driver resides outside the entity
ECE 448 – FPGA and ASIC Design with VHDL

31. Port Mode OUT c <= z z c Entity
Port signal z
Output cannot be read within the entity c
Driver resides
inside the entity
c <= z
ECE 448 – FPGA and ASIC Design with VHDL

32. Port Mode OUT (with extra signal)
Entity
Port signal x z c
Signal x can be
read inside the entity
Driver resides
inside the entity
z <= x
c <= x
ECE 448 – FPGA and ASIC Design with VHDL

33. Port Mode BUFFER z c c <= z
Entity
Port signal z c
Port signal Z can be
read inside the entity
Driver resides
inside the entity
c <= z
Not recommended by OpenCores Coding Guidelines.
Port of mode buffer can not be connected to other types of ports
so buffer mode will propagate throughout the entire hierarchical design.
Problems reported with synthesis of designs using these ports.
ECE 448 – FPGA and ASIC Design with VHDL

34. Port Mode INOUT a Entity Port signal Signal can be
read inside the entity
Driver may reside
both inside and outside
of the entity
ECE 448 – FPGA and ASIC Design with VHDL

35. Port Modes - Summary
The Port Mode of the interface describes the direction in which data travels with respect to the component
In: Data comes into this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.
Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.
Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.
Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator. Not recommended to be used in the synthesizable code.
ECE 448 – FPGA and ASIC Design with VHDL

36. Architecture (Architecture body)
Describes an implementation of a design entity
Architecture example:
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
ECE 448 – FPGA and ASIC Design with VHDL

37. Architecture – simplified syntax
ARCHITECTURE architecture_name OF entity_name IS
[ declarations ]
BEGIN
code
END architecture_name;
ECE 448 – FPGA and ASIC Design with VHDL

38. Entity Declaration & Architecture
nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE dataflow OF nand_gate IS
BEGIN
z <= a NAND b;
END dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

39. Tips & Hints Place each entity in a different file.
The name of each file should be exactly the same
as the name of an entity it contains.
These rules are not enforced by all tools
but are worth following in order to increase
readability and portability of your designs
ECE 448 – FPGA and ASIC Design with VHDL

40. Tips & Hints Place the declaration of each port,
signal, constant, and variable
in a separate line
These rules are not enforced by all tools
but are worth following in order to increase
readability and portability of your designs
ECE 448 – FPGA and ASIC Design with VHDL

41. Libraries
ECE 448 – FPGA and ASIC Design with VHDL

42. Library Declarations Library declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
Library declaration
Use all definitions from the package
std_logic_1164
ECE 448 – FPGA and ASIC Design with VHDL

43. Library declarations - syntax
LIBRARY library_name;
USE library_name.package_name.package_parts;
ECE 448 – FPGA and ASIC Design with VHDL

44. Fundamental parts of a library
PACKAGE 1
PACKAGE 2
TYPES
CONSTANTS
FUNCTIONS
PROCEDURES
COMPONENTS
TYPES
CONSTANTS
FUNCTIONS
PROCEDURES
COMPONENTS
ECE 448 – FPGA and ASIC Design with VHDL

45. Libraries ieee std work Need to be explicitly declared
Specifies multi-level logic system,
including STD_LOGIC, and
STD_LOGIC_VECTOR data types
Specifies pre-defined data types
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion
functions, basic text i/o functions, etc.
Visible by default
Holds current designs after compilation
ECE 448 – FPGA and ASIC Design with VHDL

46. STD_LOGIC Demystified
ECE 448 – FPGA and ASIC Design with VHDL

47. What is STD_LOGIC you ask?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE dataflow OF nand_gate IS
BEGIN
z <= a NAND b;
END dataflow;
What is STD_LOGIC you ask?
ECE 448 – FPGA and ASIC Design with VHDL

48. BIT versus STD_LOGIC BIT type can only have a value of ‘0’ or ‘1’
STD_LOGIC can have eight values
‘0’,’1’,’X’,’Z’,’W’,’L’,’H’,’-’
Useful mainly for simulation
‘0’,’1’, and ‘Z’ are synthesizable (your codes
should contain only these three values)
ECE 448 – FPGA and ASIC Design with VHDL

49. STD_LOGIC type demystified
Value
Meaning
‘X’
Forcing (Strong driven) Unknown
‘0’
Forcing (Strong driven) 0
‘1’
Forcing (Strong driven) 1
‘Z’
High Impedance
‘W’
Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0. Models a pull down.
‘H’
Weak (Weakly driven) 1. Models a pull up.
‘-’
Don't Care
Signals are used to connect different parts of a design. They can be thought of as “wire” in conventional sense. Every signal has a type. A type is all the valid values that a signal can assume.
VHDL naturally supports bit type, which allows signals of this (bit) type to take the values ‘0’ or ‘1’.
Signals of type integer can take integer values between +(231 – 1) to -(231-1).
Wire in real implementation may need to take an unknown value, ‘X’ or high impedance value, ‘Z’. Thus, IEEE 1164 standard defined std_logic with nine values listed in Table 1.
Std_logic_vector is an array or vector of std_logic type. It represents a bus and has dimension associated with it, which is known as the range of vector.
ECE 448 – FPGA and ASIC Design with VHDL

50. More on STD_LOGIC Meanings (1)
‘1’
‘X’
Contention on the bus X
‘0’
ECE 448 – FPGA and ASIC Design with VHDL

51. More on STD_LOGIC Meanings (2)
ECE 448 – FPGA and ASIC Design with VHDL

52. More on STD_LOGIC Meanings (3)
VDD
VDD
‘H’
‘0’
‘1’
‘L’
ECE 448 – FPGA and ASIC Design with VHDL

53. More on STD_LOGIC Meanings (4)
Do not care.
Can be assigned to outputs for the case of invalid
inputs(may produce significant improvement in resource utilization after synthesis).
Must be used with great caution.
For example in VHDL, the comparison
‘1’ = ‘-’
gives FALSE.
‘-’
ECE 448 – FPGA and ASIC Design with VHDL

54. Resolving logic levels
X Z W L H -
X X X X X X X X X
0 X X X
1 X X X
Z X Z W L H X
W X W W W W X
L X L W L W X
H X H W W H X
- X X X X X X X X
ECE 448 – FPGA and ASIC Design with VHDL

55. STD_LOGIC Rules
In ECE 448, use std_logic or std_logic_vector for all entity input or output ports
Do not use integer, unsigned, signed, bit for ports
You can use them inside of architectures if desired
You can use them in generics
Instead use std_logic_vector and a conversion function inside of your architecture
[Consistent with OpenCores Coding Guidelines]
ECE 448 – FPGA and ASIC Design with VHDL

56. Modeling Wires and Buses
ECE 448 – FPGA and ASIC Design with VHDL

57. Signals a b SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); a 1
wire b
bus 8
ECE 448 – FPGA and ASIC Design with VHDL

58. Standard Logic Vectors
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= ‘1’;
b <= ”0000”; Binary base assumed by default
c <= B”0000”; Binary base explicitly specified
d <= X”AF67”; Hexadecimal base
e <= O”723”; Octal base
ECE 448 – FPGA and ASIC Design with VHDL

59. Vectors and Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= ”0000”;
b <= ”1111”;
c <= a & b; c = ” ”
d <= ‘0’ & ” ”; -- d <= ” ”
e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’;
-- e <= ” ”
ECE 448 – FPGA and ASIC Design with VHDL

60. Fixed Rotation in VHDL A<<<1 ArotL <=
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0)
A<<<1
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
A(2)
A(1)
A(0)
A(3)
ArotL <=
ECE 448 – FPGA and ASIC Design with VHDL

61. Fixed Shift in VHDL A>>1 AshiftR <=
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0)
A>>1
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
‘0’
A(3)
A(2)
A(1)
AshiftR <=
ECE 448 – FPGA and ASIC Design with VHDL

62. VHDL Design Styles
ECE 448 – FPGA and ASIC Design with VHDL

63. VHDL Design Styles VHDL Design Styles behavioral dataflow structural
Testbenches
dataflow
behavioral
(sequential)
structural
Concurrent
statements
Components and
interconnects
Sequential statements
Registers
State machines
Decoders
Subset most suitable for synthesis
ECE 448 – FPGA and ASIC Design with VHDL

64. xor3 Example
ECE 448 – FPGA and ASIC Design with VHDL

65. Entity xor3_gate LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor3_gate IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC );
end xor3_gate;
ECE 448 – FPGA and ASIC Design with VHDL

66. Dataflow Architecture (xor3_gate)
ARCHITECTURE dataflow OF xor3_gate IS
SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1_OUT <= A XOR B;
Result <= U1_OUT XOR C;
END dataflow;
U1_OUT
ECE 448 – FPGA and ASIC Design with VHDL

67. Dataflow Description
Describes how data moves through the system and the various processing steps.
Dataflow uses series of concurrent statements to realize logic.
Dataflow is most useful style when series of Boolean equations can represent a logic  used to implement simple combinational logic
Dataflow code also called “concurrent” code
Concurrent statements are evaluated at the same time; thus, the order of these statements doesn’t matter
This is not true for sequential/behavioral statements
This order…
U1_out <= A XOR B;
Result <= U1_out XOR C;
Is the same as this order…
ECE 448 – FPGA and ASIC Design with VHDL

68. Structural Architecture in VHDL 87
ARCHITECTURE structural OF xor3_gate IS
SIGNAL U1_OUT: STD_LOGIC;
COMPONENT xor2
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC );
END COMPONENT;
BEGIN
U1: xor2 PORT MAP (I1 => A,
I2 => B,
Y => U1_OUT);
U2: xor2 PORT MAP (I1 => U1_OUT,
I2 => C,
Y => Result);
END structural; A B C
Result
xor3_gate
U1_OUT I1 I2 Y I1 I2 Y
PORT NAME
LOCAL WIRE NAME
ECE 448 – FPGA and ASIC Design with VHDL

69. xor2 xor2.vhd LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END xor2;
ARCHITECTURE dataflow OF xor2 IS
BEGIN
Y <= I1 xor I2;
END dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

70. Structural Architecture in VHDL 93
ARCHITECTURE structural OF xor3_gate IS
SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1: entity work.xor2(dataflow)
PORT MAP (I1 => A,
I2 => B,
Y => U1_OUT);
U2: entity work.xor2(dataflow)
PORT MAP (I1 => U1_OUT,
I2 => C,
Y => Result);
END structural; A B C
Result
xor3_gate
U1_OUT I1 I2 Y I1 I2 Y
PORT NAME
LOCAL WIRE NAME
ECE 448 – FPGA and ASIC Design with VHDL

71. Structural Description
Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.
Components are interconnected in a hierarchical manner.
Structural descriptions may connect simple gates or complex, abstract components.
Structural style is useful when expressing a design that is naturally composed of sub-blocks.
ECE 448 – FPGA and ASIC Design with VHDL

72. Behavioral Architecture (xor3 gate)
ARCHITECTURE behavioral OF xor3 IS
BEGIN
xor3_behave: PROCESS (A, B, C)
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS xor3_behave;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

73. Behavioral Description
It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).
This style uses PROCESS statements in VHDL.
ECE 448 – FPGA and ASIC Design with VHDL

74. ?
ECE 448 – FPGA and ASIC Design with VHDL