1. Advisor: Jin-Fu Li TA: Shin-Yo Lin
National Central University
EE 613 VLSI Design
EE 613 VLSI Design
Advisor: Jin-Fu Li
TA: Shin-Yo Lin
2002/9/23

2. National Central University
EE 613 VLSI Design
Schedule
Date
Function
9/23
Project proposal
9/30
DFF/1 Bit ALU (Adder)
Layout/PostSim
10/7
Module Verilog & Module Layout
10/14
System Verilog & All Block Layout
10/21
Integrated
10/28
11/4
Tapeout
2002/9/23

3. National Central University
EE 613 VLSI Design
Requirement
You can assign project by yourself (Gate counts at least 5K).
The two persons enjoy project.
Submit to sub-module reports per week.
Oral Presentation
Briefly explain your sub-module reports and progress by a week.
Simulation, Waveform, Layout.
2002/9/23

4. National Central University
EE 613 VLSI Design
Design Flow
Verilog
HSPICE
PDRACULA
GDSII File
Chip Specification
Simulation & Comparison
Circuit Design
Layout
Verification
2002/9/23

5. National Central University
EE 613 VLSI Design
CPU Block Diagram
4 to 16 Instruction Decoder
8-bit Register A
8-bit Register B
8-bit Register C
8-bit
ALU
64 byte SRAM
Some MUX
&
control logic
2002/9/23

6. National Central University
EE 613 VLSI Design
Instruction Sets
2002/9/23

7. National Central University
EE 613 VLSI Design
Chip Implementation
CIC 0.35m education chip available areas are 1500m×1500m, take off area of 28 PAD remain 748m×748m.
2002/9/23

8. National Central University
EE 613 VLSI Design
Proposal Format
14 pt
12 pt
NO MORE THAN TWO PAPERS!!
2002/9/23