1. Design Methodology & HDL
黃俊傑

6. Design Methodology

7. HDL - Hardware Description Language
VHDL & Verilog (IEEE standard)
Define Specification
Design Description
Function Verification
Logic synthesis
Gate-Level Netlist Verification
Place and Routing
Post Layout Verification

8. HDL vs. other Language (1)
Parallel & sequence block concept B1 A B2 C B3

9. HDL vs. other Language (1a)
block concept
Combination circuit function
→ without F/F
Sequence circuit function
→ with F/F ( memory characteristic )
Mix (1) and (2) into block concept
F/F
Input C
Output

10. HDL vs. other Language (2)
Timing concept A B C A C

11. HDL vs. other Language (3)
Event trigger concept A B D C A C D

12. HDL vs. other Language (3a)
Synchronous design concept
Input_N B
Output
Clock
Input_N
Clock
Output

13. HDL vs. Finite state machine
Idle_st
A1_i
FSM1_st
A1_o
A2_i
FSM2_st
A2_o
A3_i
FSM3_st
A3_o
Done

14. Verilog HDL – Level Property
Transistor Level (Model)
Gate Level Model (Model)
Register Transfer Level
Behavioral Level

15. Electronics System Level Design
System C & System Verilog ( ESL )
Define Specification (+)
Design Description (+)
Function Verification (+)
Logic synthesis (-)
Gate-Level Netlist Verification (-)
Place and Routing (-)
Post Layout Verification (-)