1. Review: The whole processor
Control Unit
Datapath D
Register file
A B WR DA AA BA
A B
ALU G FS V C N Z
Mux B MB
Mux D MD
ADRS DATA
Data RAM
OUT MW
constant
ADRS
Instruction
RAM
OUT PC
Instruction Decoder
DA AA BA MB FS MD WR MW
Branch
Control V C N Z
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2. What must the control unit do:
On each clock cycle:
1. An instruction is read from the instruction memory.
2. The instruction decoder generates the matching datapath control word.
3. Datapath registers are read and sent to the ALU or the data memory.
4. ALU or RAM outputs are written back to the register file.
The PC is incremented, or reloaded for branches and jumps.
ADRS
Instruction
RAM
OUT PC
Instruction Decoder
DA AA BA MB FS MD WR MW
Branch
Control V C N Z
Today, we show how to implement the two components of the Control Unit :
The Instruction Decoder and
The Branch Control Unit
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Instruction encoding

3. I: Implementing the instruction decoder
The first thing we’ll look at is how to build the instruction decoder.
The instruction decoder’s input is a 16-bit binary instruction I that comes from the instruction memory.
The decoder’s output is a control word for the datapath. This includes:
WR, DA, AA, BA, and MD signals to control the register file.
FS for the ALU operation.
MW for the data memory write enable.
MB for selecting the second operand.
We’ll see how these signals are generated for each of the three instruction formats.
ADRS
Instruction
RAM
OUT
Instruction Decoder
DA AA BA MB FS MD WR MW
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4. MB, MD, WR and MW
The following table shows the correct signals MB, MD, WR and MW for each of the eight different instruction categories we defined.
As mentioned last time, this is the sense in which these categories contain “similar” instructions.
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Instruction encoding

5. Eight categories of instructions
There are several patterns visible in this table.
MW = 1 only for memory write operations.
MB = 1 only for immediate instructions, which require a constant.
MD is unused when WR = 0.
Jumps and branches modify neither registers nor main memory.
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Instruction encoding

6. Generating MB, MD, WR, and MW
Because of the way we defined our opcodes, the four control signals MB, MD, WR and MW can be expressed as functions of the first three opcode bits, or instruction bits I15, I14 and I13.
MB = I15 MD = I14
WR = I14’ + I15’ I13 MW = I15’ I14 I13’
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7. Generating FS
Yesterday, we used an ALU function selector as the last four bits in the opcode of ALU and shift instructions.
For example, a register-based XOR has the opcode
The first three bits 000 indicate a register-based ALU instruction.
1100 is the ALU code for the XOR function.
Thus, the control unit can “generate” the ALU’s FS control signal just by taking it directly out of the instruction opcode.
For register and immediate-format instructions: 5 FS
FS4 FS3 FS2 FS1 FS0 = I13 I12 I11 I10 I9
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8. FS for branch instructions
FS would be don’t-cares for loads, stores and jumps, which do not involve the ALU.
However, FS is required for branch instructions, which depend on the ALU’s status bit outputs.
For example, in
BZ R3, -24
the contents of R3 must go through the ALU so that Z will be set appropriately.
For our branches, we just need the ALU function “G = A” (FS = or 00111). D
Register file
A B WR DA AA BA
A B
ALU G FS V C N Z
Mux B MB
Mux D MD
ADRS DATA
Data RAM
OUT MW
constant
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9. Generating DA, AA, BA
The register file addresses DA, AA and BA can be taken directly out of the 16-bit binary instructions.
Instruction bits 8-6 are the destination register, DA.
Bits 5-3 are fed directly to AA, the first register file source.
Bits 2-0 are connected directly to BA, the second source.
This clearly works for a register-format instruction where bits 8-6, 5-3 and 2-0 were defined to hold the destination and source registers. D
Register file
A B WR DA AA BA 3 DA AA BA
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10. Don’t-care conditions
In immediate-format instructions, bits 2-0 store a constant operand, not a second source register!
However, immediate instructions only use one source register, so the control signal BA would be a don’t care condition anyway.
Similarly, jump and branch instructions require neither a destination register nor a second source register.
So we can always take DA, AA and BA directly from the instruction. 3 DA AA BA
DA2 DA1 DA0 = I8 I7 I6
AA2 AA1 AA0 = I5 I4 I3
BA2 BA1 BA0 = I2 I1 I0
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Instruction encoding

11. II: Designing branch control unit
Next, let’s see how to manage the control flow of a program.
The branch control unit needs a lot of information about the current instruction.
Whether it’s a jump, a branch, or some other instruction.
For branches and jumps, the target address.
For branches, the specific branch condition.
All of this can be generated by the instruction decoder, which has to process the instruction words anyway.
ADRS
Instruction
RAM
OUT PC
Instruction Decoder
DA AA BA MB FS MD WR MW
Branch
Control V C N Z
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12. Branch control unit inputs and outputs
Branch control inputs:
PL, JB, BC and AD are output by the instruction decoder, and carry information about the current instruction.
Status bits V, C, N and Z come from the datapath.
The current PC is needed for PC-relative mode jumps and branches.
Branch control outputs:
A Load signal for the PC.
When Load = 1, the branch control unit also generates the target address to jump or branch to.
ADRS
Instruction
RAM
OUT PC
Instruction Decoder
DA AA BA MB FS MD WR MW
Branch
Control V C N Z
PL JB BC AD
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13. Branch control unit inputs
The decoder sends the following data to the branch control unit:
PL and JB indicate the type of instruction.
BC encodes the kind of branch.
AD determines the jump or branch target address.
ADRS
Instruction
RAM
OUT PC
Instruction Decoder
DA AA BA MB FS MD WR MW
Branch
Control V C N Z
PL JB BC AD
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14. Generating PL and JB
The instruction decoder generates PL and JB from instruction opcodes.
Note that if PL = 0, then the value of JB doesn’t matter.
As expected, PL and JB only matter for jumps and branches.
From this table you could derive:
PL = I15 I14 JB = I13
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15. Generating BC and AD
We defined the branch opcodes so that they already contain the branch type, so BC can come straight from the instruction.
AD can also be taken directly out of the instruction. 3 BC AD
BC2 BC1 BC0 = I11 I10 I9
AD5 AD4 AD3 AD2 AD1 AD0 = I8 I7 I6 I2 I1 I0
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16. Branch control unit
Now we’ve seen how the instruction decoder generates PL, JB, BC and AD. How does the branch unit use these to control the PC?
There are three cases, depending on the values of PL and JB.
If PL = 0, the current instruction is not a jump or branch, so the branch control just needs to make the program counter increment, and execute the next instruction. PC
Branch
Control V C N Z
PL JB BC AD
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17. Jumps If PL = 1 and JB = 1, the current instruction must be a jump.
We assume PC-relative addressing, so the jump “offset” (AD) must be added to the current PC value, and then stored back into the PC.
The branch control unit would contain an adder just for computing the target address.
Again, AD is signed so we can jump forwards or backwards. PC
Branch
Control V C N Z
PL JB BC AD
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18. Branches
If PL = 1 and JB = 0, the current instruction is a conditional branch.
The branch control unit first determines if the branch should be taken.
It checks the type of branch (BC) and the status bits (VCNZ).
For example, if BC = 011 (branch if zero) and Z = 1, then the branch condition is true and the branch should be taken.
Then the branch control unit sets the PC appropriately.
If the branch is taken, AD is added to the PC, just as for jumps.
Otherwise, the PC is incremented, just as for normal instructions. PC
Branch
Control V C N Z
PL JB BC AD
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19. Summary Today we saw an outline of the control unit hardware.
The program counter points into a special instruction memory, which contains a machine language program.
An instruction decoder looks at each instruction and generates the correct control signals for the datapath and a branching unit.
The branch control unit handles instruction sequencing.
The control unit implementation depends on both the instruction set architecture and the datapath.
Careful selection of opcodes and instruction formats can make the control unit simpler.
In MP4 you’ll design the control unit for a slightly different CPU.
We now have a whole processor! This is the culmination of everything we did this semester, starting from those tiny little primitive gates.
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Instruction encoding