1. Page Table Implementations
CSCE 410/611
Page Table Implementations
Issues in implementing the page table
Multi-level page table
Inverted page table
Hashed page table
Page Table Implementations

2. Implementation of Page Table
CSCE 410/611
Implementation of Page Table
Observation: Page table must store one entry per page.
Question: How to store the page table?
Naïve solution: Store page table as array in memory.
Page-Table-Base-Register (PTBR) points to start of array.
New PTBR loaded during address space switch.
PTBR
Problem: Page table can become very large.
Example: 32-bit address space (4GB), 4kB pages, 4B entries
=> 220 entries in page table
=> we need 4MB per process (!)
Page Table Implementations

3. Hierarchical (Multilevel) Paging
CSCE 410/611
Hierarchical (Multilevel) Paging
Problem: Page tables can become very large!
Observation: Most of the address space is not used.
=> Most of the page table is empty.
Solution: Page the page table!
page table nr.
page table
page nr.
offset
PTBR f d f
Page Table Implementations

4. Hierarchical (Multilevel) Paging
CSCE 410/611
Hierarchical (Multilevel) Paging
Example: Two-level Paging (x86)
page table nr. (10)
page nr. (10)
offset (12)
PTBR f d f
Page Table Implementations

5. Hierarchical (Multilevel) Paging
CSCE 410/611
Hierarchical (Multilevel) Paging
Example: Three-level Paging (SPARC)
1st level dir
2nd level dir
page nr.
offset
PTBR f d f
Page Table Implementations

6. Hierarchical (Multilevel) Paging
CSCE 410/611
Hierarchical (Multilevel) Paging
Example: Four-level Paging (68030)
1st level dir
2nd level dir
3rd level dir
page nr.
offset
PTBR f d f
Page Table Implementations

7. Variations: Inverted Page Table
CSCE 410/611
Variations: Inverted Page Table
Pros:
Scales with physical memory
One table for whole system
proc id
page no
offset
process id
page no 1 2 3 … n
Cons:
Long search times for large physical memories 3
offset
address resolution: search for matching frame entry
Array of page entries, indexed by frame number
Used in early virt. memory systems, such as the Atlas computer.
Page Table Implementations

8. Variations: Hashed Page Table
CSCE 410/611
Variations: Hashed Page Table
Used by many 64bit architectures:
IBM POWER, HP PA-RISC, Itanium
proc id
page no
offset
hash function f d
Pros:
Scales with physical memory
One table for whole system
proc id
page no
frame no
chain f
Cons:
How about collisions?
Page Table Implementations

9. Summary Page table size is an issue for large address spaces.
CSCE 410/611
Summary
Page table size is an issue for large address spaces.
Multi-level page table
Inverted page table
Hashed page table
Page Table Implementations