1. Timing Analysis and Optimization of Sequential Circuits
中原大學 電子系
黃世旭

2. Outline Introduction Path Analysis Clock Analysis Timing Optimization
Why Timing Analysis
Design Compiler’s Timing Analyzer
Path Analysis
False Path
Hierarchical Timing Analysis with False Path
Clock Analysis
Clock Distribution Network
Timing Analysis for Registers
Timing Analysis for Latches
Timing Analysis for Domino Logics
Timing Optimization
Clock Skew Optimization
Retiming

3. Why Timing Analysis？
Continuing advances in design techniques and fabrication process technology are resulting in the design and manufacture of very high speed digital systems.
Digital system operation at high clock speeds does not allow for much design margin, so these circuits have to be designed under very tight timing constraints.
In such a scenario, it is imperative to verify the temporal behavior of such circuit designs before they are sent for fabrication.
Continuing advances in design techniques and fabrication process technology are resulting in the design and manufacture of very high speed digital systems. Digital system operation at high clock speeds does not allow for much design margin, so these circuits have to be designed under very tight timing constraints.In such a scenario, it is imperative to verify the temporal behavior of such circuit designs before they are sent for fabrication.

4. Sequential Circuit
Over the years, considerable work has been done in high-level timing verification, e.g., at the behavioral level, the structural RTL level, etc. Work has also been done at sequential circuit level of abstraction where a circuit is viewed as levels of latches or flip-flops separated by clouds of combinational logic.

5. Timing Analysis for Sequential Circuit
Determining the minimum and maximum delays of the individual combinational clouds of logic.
Finding the minimum feasible clock period by treating these combination clouds of logic as monolithic blocks.
This is very complex problem, especially in cases when the design is asynchronous, or when transparent latches which enable cycle stealing(also called time borrowing) are used in design. Because of this, researchers have tended to view the problem of determining the minimum cycle time for a sequential circuit as consisting of two parts - determining the minimum and maximum delays of the individual combinational clouds of logic, and then finding the minimum feasible clock period by treating these combination clouds of logic as monolithic blocks.

6. Zero Clock Skew Suppose that the clock period is 2. The circuit fails!
Assume each of the inverters to have a unit delay. This circuit cannot be properly clocked to function at a period of 2 time units, because as shown in the Figure, the required arrival time of the signal at register F1 is 2 units, while the data arrives after 3 time units. It is readily verifiable that the fastest allowable clock for this circuit has a period of 3 units.

7. The Advantage of Non-Zero Skew
Suppose that the clock period is 2.
The circuit works!
The application of a skew of +1 unit delays the clock arrival at register F1 by one unit, thus changing the required data arrival time to the new arrival time of the first clock tick, which is 3 units (i.e., the period of 2 unit delayed by +1 unit). Under these circumstances, the actual data arrival time of 3 units does not cause a timing violation, and the circuit is correctly clocked.

8. Clock Skew
Clock Skew: Tskew i,j=ci - cj
Tskew i,j=ci - cj

9. Positive Clock Skew Positive Clock Skew: ci ≧ cj
Tskew i,j= ci – cj ≧ 0

10. Negative Clock Skew
Negative Clock Skew:
ci < cj
Tskew i,j = ci – cj < 0
Negative clock skew subtracts from the logic path delay!

11. Enhancing Performance by Applying Non-Zero Skew
Applying negative clock skew can increase the total time that a local data path has to accomplish its functional requirements.
Therefore, non-zero skew approach can be used to improve performance by providing more time for the critical worst case data paths.
Applying negative clock skew can increase the total time that a local data path has to accomplish its functional requirements. Therefore, non-zero skew approach can be used to improve performance by providing more time for the critical worst case data paths.

12. assume registers delay=2
Example
Example
assume registers delay=2

13. Example
Example

14. Local Data Path
Local Data Path

15. The constraint on negative clock skew
Double Clocking
Double-clocking/Short path constraint:
To avoid double-clocking, the data from the next clock cycle should arrive at Rj no earlier than a time Thold after the current clock. The data leaves Ri at time ci and, therefore, the earliest time it can reach Rj is ci + d(i,j).
The constraint on negative clock skew

16. The constraint on positive clock skew
Zero Clocking
Zero-Clocking/Long path constraint
To avoid zero- clocking , the data from the current clock cycle should arrive at Rj no later than a time Tsetup before the next clock. Since the data leaves Ri at time ci, the latest time by which it will reach Rj is ci + d(i,j).
The constraint on positive clock skew

17. Clock Skew Optimization
minimize P
such that for each Ri Rj
The problem of minimizing the clock period p by controlling the clock skew at each flip-flop, subject to correct timing, can be formulated as the linear program. The linear program assumes that the delays of the combinational segments are constant.

18. Graph Model of a Circuit
A vertex iV(G) represents a register and a edge (i,j)E(G) does the signal transmission from register i to register j along functional elements of the circuit.
The weight of edge (i,j) is a pair (d(i,j),d(i,j)) where d(i,j) and d(i,j) are the minimum and maximum signal propagation delays, respectively.
A vertex iV(G) represents a register and a edge (i,j)E(G) does the signal transmission from register i to register j along functional elements of the circuit. The weight of edge (i,j) is a pair (d(i,j),d(i,j)) where d(i,j) and d(i,j) are the minimum and maximum signal propagation delays, respectively.

19. Example
Example

20. Circuit Graph
Circuit Graph

21. Constraint Graph
The constraint graph is obtained from the graph model of the circuit by replacing each edge (i,j) with a D-edge (i,j) and a Z-edge (j,i).
Double clocking constraint:
Zero clocking constraint:
The constraint graph is obtained from the graph model of the circuit by replacing each edge (i,j) with a D-edge (i,j) and a Z-edge (j,i).
Double clocking constraint:
Tskew i,j ≧ Thold – d(i,j)
Zero clocking constraint:
Tskew j,i ≧ – P + d(i,j)+Tsetup

22. Constraint Graph
Constraint Graph

23. Constraint Graph
The clock period P is feasible, provided the corresponding constraint graph contains no positive cycles.
If P is achievable, then a set of skews that satisfies P can be found by solving the longest path problem on this directed graph.
The clock period P is feasible, provided the corresponding constraint graph contains no positive cycles. If P is achievable, then a set of skews that satisfies P can be found by solving the longest path problem on this directed graph.

24. Bellman-Ford Algorithm
The Bellman-Ford algorithm may be applied to solve a single-source longest path problem on a directed graph. Unlike Dijskstra-like algorithms, it can handle edge weights of either sign, but has a higher computational complexity. The pseudocode for the application of the algorithm to a graph G = (V,E,w), where V and E are the set of vertices and edges, respectively, of the graph, and w is the vector of edge weights.

25. Lower Bound of Clock Period
for each Ri Rj
A lower bound, Plow, on the value of the optimal clock period is given by
Where the max operates on all pairs(i,j) of FF’s that are connected by a combinational path.

26. Upper Bound of Clock Period
If the original circuit satisfies all short path constraints, then an upper bound, Phigh on the value of the optimal clock period is given by
As before, the max operates on all pairs (i,j) of FF’s that are connected by a combinational path.

27. Binary Search for Optimal Clock Period
The optimal clock period is obtained by performing a binary search. At each step in the binary search (for clock period P) the constraint feasible clock for positive cycles. The procedure continues until the smallest feasible clock period is found. The following skeletal pseudocode is used to perform the binary search for the optimal clock period.

28. Is Clock Skew Optimization Safe?
It is a misconception to believe that zero skew is entirely safe.
It is a misconception to believe that clock skew optimization is unsafe.
It is a misconception to believe that zero skew is entirely safe. In fact, this is not so; one can build in safety margins. These safety margins ensure that the circuit will operate in the presence of unintentional process-dependent skew variations. Introducing deliberate delays within the clocking network has been a tactic that has long been used by designers.
It is a misconception to believe that clock skew optimization is unsafe.

29. The Perils of Zero Skew
In fact, to see this, consider a shift register consisting of register A whose output is connected to register B with no combinational logic between the two, as show in Figure. Even for a circuit designed for zero skew, a small unintentional positive skew at register B will cause double-clocking, i.e., a short path constraint violation.
A small unintentional positive skew at register B will cause double clocking!

30. Modeling Uncertainties in Clock Skew Optimization
The above formulation may be altered to model uncertainties in the clock skews. If it can be guaranteed that in the manufactured circuit. The skew at flip-flop k will be within the range[ck-δ/2,ck+δ/2], where ck is the designed value of the skew, then the difference between any skews, (ci - cj) in the manufactured circuit, must be within δ of the designed value of (ci - cj).

31. Modeling Uncertainties in Clock Skew Optimization
minimize P
such that for each Ri Rj
Modeling uncertainties in clock skew optimization.

32. Maximizing the Tolerance
An alternative formulation to maximize the tolerance to unpredictable changes for a given clock period P.
A new variable δ is introduced, and is added to each of the main constraint inequalities, so that maximizing δ is tantamount to finding the skew values that maximize the minimum slack over all the inequalities.
An alternative formulation to maximize the tolerance to unpredictable changes for a given clock period P. This may be achieved by maximizing the minimum slack over all the constraints, converting the problem into a minmax problem. A new variable δ is introduced, and is added to each of the main constraint inequalities, so that maximizing δ is tantamount to finding the skew values that maximize the minimum slack over all the inequalities.

33. Maximizing the Tolerance to Uncertainties
Maximize δ
such that for each Ri Rj
Maximizing the tolerance to uncertainties.

34. Conclusions
Maximizing the tolerance to uncertainties.