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Computer Concept and Practice
Basic Computer Architecture & Instruction Types
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Basic Computer Architecture
Memory CPU 32bits Registers 000000···000 Operation Unit (Arithmetic /Logic Unit : ALU) PC R0 R1 R31 4GB = 2 bytes 32bits 32 Memory Contains instructions and data CPU Repeat the following two steps 1) Fetch an instruction 2) Execute the instruction Register PC : indicates the memory address of the currently executing instruction Others : "General Purpose" registers 111111···111 8bits
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Instruction Types (가) Arithmetic & Logic Instruction
OP Source Register 1 Source Register 2 Destination Register (가) Arithmetic & Logic Instruction 8bits 5bits 5bits 5bits OP Source Register Destination Register Constant (가)’ Arithmetic & Logic Instruction 8bits 5bits 5bits 14bits OP Destination Register Register # Constant (나) Load Instruction (Memory -> Register) 8bits 5bits 14bits 5bits OP Source Register Register # Constant (다) Store Instruction (Register -> Memory) 8bits 5bits 14bits 5bits OP Register #1 Register #2 Constant (라) Branch Instruction 8bits 5bits 5bits 14bits OP Register # (마) Jump Instruction 8bits 5bits
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Arithmetic & Logic Instruction(1/2)
OP Source Register 1 Source Register 2 Destination Register (가) Arithmetic & Logic Instruction 8bits 5bits 5bits 5bits ADD 00001 00010 00100 Ex) ADD R1, R2, R4 Registers R0 4 6 2 7 1 · · · + R1 R2 R3 R4 10 R5
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Arithmetic & Logic Instruction(2/2)
OP Source Register Destination Register Constant (가)’ Arithmetic & Logic Instruction 8bits 5bits 5bits 14bits ADD’ 00100 00010 Ex) ADD’ R4, R2, 16 Registers R0 4 6 2 10 1 · · · + R1 R2 26 R3 R4 R5
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Load Instruction + 7 13 OP Constant
Destination Register Register # Constant (나) Load Instruction (Memory -> Register) 8bits 5bits 14bits 5bits LOAD 00011 00000 Ex) LOAD R3, 4( R0 ) Memory · · · 00···0000 Registers 7 00···0001 R0 4 20 2 10 1 · · · 00···0010 R1 00···0011 + R2 00···0100 R3 13 00···0101 13 R4 00···0110 R5 00···0111
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Store Instruction + 10 7 13 OP Constant
Source Register Register # Constant (다) Store Instruction (Register -> Memory) 8bits 5bits 14bits 5bits STORE 00100 00000 Ex) STORE R4, 0( R0 ) Memory · · · 00···0000 Registers 7 10 00···0001 R0 4 20 13 10 1 · · · 00···0010 R1 00···0011 + R2 00···0100 R3 00···0101 13 R4 00···0110 R5 00···0111
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Branch Instruction(1/2)
OP Register #1 Register #2 Constant (라) Branch Instruction 8bits 5bits 5bits 14bits Memory · · · BGE BLE LOAD BGE 00000 00010 Ex1) BGE R0, R2, 12 A A+1 A+2 A+3 R0 4 20 13 10 1 · · · 4 PC A A+4 R1 >=? A+5 A+6 R2 YES NO A+7 R3 A+8 R4 + A+9 R5 A+10 A+11 Registers
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Branch Instruction(1/2)
OP Register #1 Register #2 Constant (라) Branch Instruction 8bits 5bits 5bits 14bits Memory · · · BGE BLE LOAD BGE 00000 00010 Ex1) BGE R0, R2, 12 A A+1 A+2 A+3 R0 4 20 13 10 1 · · · 4 PC A + 4 A A+4 R1 >=? A+5 A+6 R2 YES NO A+7 R3 A+8 R4 + A+9 R5 A+10 A+11 Registers
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Branch Instruction(2/2)
OP Register #1 Register #2 Constant (라) Branch Instruction 8bits 5bits 5bits 14bits Memory · · · BGE BLE LOAD BLE 00000 00011 Ex2) BLE R0, R3, 20 A A+1 A+2 A+3 R0 4 20 13 10 1 · · · 4 A + 4 A+4 PC R1 <=? A+5 A+6 R2 YES NO A+7 R3 A+8 + R4 A+9 R5 A+10 A+11 Registers
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Branch Instruction(2/2)
OP Register #1 Register #2 Constant (라) Branch Instruction 8bits 5bits 5bits 14bits Memory · · · BGE BLE LOAD BLE 00000 00011 Ex2) BLE R0, R3, 20 A A+1 A+2 A+3 R0 4 20 13 10 1 · · · 4 A + 4 A + 24 A+4 PC R1 <=? A+5 A+6 R2 YES NO A+7 R3 A+8 + R4 A+9 R5 A+10 A+11 Registers
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Jump Instruction (마) Jump Instruction OP JUMP 8bits 5bits Ex) JUMP R2
Register # (마) Jump Instruction 8bits 5bits Memory JUMP 00010 Ex) JUMP R2 · · · ADD’ JUMP 00010*** ******** 20 21 Registers 22 R0 4 20 13 10 1 · · · A + 24 PC 23 R1 R2 A+24 R3 A+25 R4 A+26 R5 A+27
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Jump Instruction (마) Jump Instruction OP JUMP 8bits 5bits Ex) JUMP R2
Register # (마) Jump Instruction 8bits 5bits Memory JUMP 00010 Ex) JUMP R2 · · · ADD’ JUMP 00010*** ******** 20 21 Registers 22 R0 4 20 13 10 1 · · · 20 A + 24 PC 23 R1 R2 A+24 R3 A+25 R4 A+26 R5 A+27
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