1. Translation Lookaside Buffers
CSCE 410/611
Translation Lookaside Buffers
Page table lookups are expensive!
Caching of page table entries
Translation Lookaside Buffers (TLBs)
Software-managed TLBs: MIPS
TLBs

2. Recall: Address Translation for Two-Level Paging
CSCE 410/611
Recall: Address Translation for Two-Level Paging
Physical Memory
MMU
CPU
page table nr.
page nr.
offset
PTBR f d f
TLBs

3. Recall: Address Translation for Two-Level Paging
CSCE 410/611
Recall: Address Translation for Two-Level Paging
Physical Memory
MMU
CPU
page table nr.
page nr.
offset f d
PTBR f
TLBs

4. Solution: Translation Lookaside Buffers
CSCE 410/611
Solution: Translation Lookaside Buffers
Physical Memory
MMU
CPU
page table nr.
page nr.
offset f d
Translation lookaside buffer (TLB)
page nr.
frame nr. f
PTBR f
“input”
“output”
TLBs

5. Memory Translation with a TLB
CSCE 410/611
Memory Translation with a TLB
page nr.
frame nr. f
Split virtual address, use page number.
Look in the TLB to see if we find translation entry for page.
If YES, use frame number.
If NO, system must locate page entry in main-memory-resident page table, load it into TLB, and start again.
TLBs

6. Parameters of the TLB Parameters of TLBs Size: 12 – 4096 entries
CSCE 410/611
Parameters of the TLB
page nr.
frame nr. f
Parameters of TLBs
Size: 12 – 4096 entries
Lookup latency: 0.5 – 1 clock cycles
Miss penalty: 10 – 100 clock cycles
Target miss rate: 0.01% – 1%
TLBs

7. Freeing TLB Entries Page Table MMU f CSCE 410/611 TLBs Logical Memory
Physical Memory
MMU
Page Table
PTBR
frame f
page p f
TLBs

8. Freeing TLB Entries p f Page Table MMU f CSCE 410/611 TLBs
Logical Memory
Physical Memory
MMU
Page Table
PTBR
frame f
page p f
TLB
page nr.
frame nr. p f
TLBs

9. Freeing TLB Entries ? p f Page Table MMU CSCE 410/611 TLBs
Logical Memory
Physical Memory
MMU
Page Table
PTBR
TLB
Flush TLB entry
page nr.
frame nr. ? p f
TLBs

10. How many TLBs? One TLB per address space (process)
CSCE 410/611
How many TLBs?
One TLB per address space (process)
Need to flush TLB for every process switch.
page nr.
frame nr. f
One TLB for entire system
address space id
page nr.
frame nr. f
TLBs

11. Software-Managed TLBs: Paging - MIPS Style
CSCE 410/611
Process no.
Program (virtual) address
ASID
VPN (virtual page number)
Address within page
System-wide TLB
ASID
VPN
PFN
Flags
Physical address
PFN (physical frame number)
Address within frame
TLBs

12. Software-Managed TLBs: Paging - MIPS Style
CSCE 410/611
Software-Managed TLBs: Paging - MIPS Style
Process no.
Program (virtual) address
ASID
VPN (virtual page number)
Address within page
TLB refill exception!
System-wide TLB
no match?!
Physical address
TLBs

13. Software-Managed TLBs: Paging - MIPS Style
CSCE 410/611
Software-Managed TLBs: Paging - MIPS Style
Process no.
Program (virtual) address
ASID
VPN (virtual page number)
Address within page
TLB refill exception!
System-wide TLB
Page table (in memory)
ASID
VPN
PFN
Flags
PFN
Flags
refill
Physical address
TLBs

14. Software-Managed TLBs: Paging - MIPS Style
CSCE 410/611
Process no.
Program (virtual) address
ASID
VPN (virtual page number)
Address within page
System-wide TLB
ASID
VPN
PFN
Flags
Physical address
PFN (physical frame number)
Address within frame
TLBs

15. Memory Translation -- MIPS Style
CSCE 410/611
Memory Translation -- MIPS Style
Principle: Make do with as little hardware as possible.
Apart from a register with the ASID, the MMU is just the TLB.
The rest is all implemented in software!
When TLB cannot translate an address, a special exception (TLB refill) is raised.
Software then takes over.
Page table (in memory)
System-wide TLB
VPN
ASID
PFN
Flags
refill
TLBs

16. Software managed TLBs: TLB Refill Exception
CSCE 410/611
Software managed TLBs: TLB Refill Exception
Figure out if this virtual address is valid.
If not, trap to handling of address errors.
If address is valid, construct TLB entry.
If TLB already full, select an entry to discard.
Write the new entry into the TLB.
Page table (in memory)
System-wide TLB
VPN
ASID
PFN
Flags
refill
TLBs

17. The MIPS TLB: TLB Entry Fields
CSCE 410/611
The MIPS TLB: TLB Entry Fields
input
output
VPN
ASID G
PFN
Flags N D V
VPN: Virtual page number
ASID: identifies the address space
G: if set, disables the matching with the ASID
PFN: Physical frame number
N: cacheable / non-cacheable
D: “write-control” bit (set to 1 if writeable)
V: valid bit
Page table (in memory)
System-wide TLB
VPN
ASID
PFN
Flags
refill
TLBs

18. TLBs: Summary Translation Lookaside Buffers (TLBs)
CSCE 410/611
TLBs: Summary
Translation Lookaside Buffers (TLBs)
Page table lookups are expensive!
Caching of page table entries
Hardware-managed vs. Software-managed TLBs
TLBs on the MIPS
TLBs