1. Mixed-Mode BIST Based on Column Matching
Petr Fišer

2. Outline Introduction to BIST State-of-the-art Methods Mixed-Mode BIST
Column-Matching Method
Experimental Results
A Summary of That Everything
Conclusions
What Could Be Done Yet

3. Introduction to BIST The BIST Structure Generate test patterns
Apply the patterns to the circuit
Evaluate the response

4. Present BIST Method Mixed-Mode BIST
Combination of pseudo-random and deterministic BIST
The easy-to-detect faults are detected by pseudo-random patterns
Some patterns are generated deterministically, to detect the hard-to-detect faults

5. State-of-the-art Methods
Reseeding
The pseudo-random test patterns are generated by LFSR, more LFSR seeds are applied
Weighted Pattern BIST
Change the probability of occurrence of 1s and 0s in the PR sequence
Bit-Fixing, Bit-Flipping, Row-matching
Modify the PR patterns by additional logic

6. Mixed-Mode BIST Combination of pseudo-random and deterministic BIST
Two disjoint phases
Simple control logic
Simple design process

7. Column-Matching LFSR produces code words
These have to be transformed into deterministic patterns (computed by ATPG)
=> Output Decoder

8. Column-Matching Basic Principle
Try to reorder test patterns, so that most of the Decoder outputs will be implemented as wires – A Column Match
This will be accomplished when the particular columns of the LFSR and test matrix will be equal
Direct match – even the Switch logic is eliminated

9. Column-Matching Example y0 = x4’ + x1 y1 = x3’ y2 = x2 x3’ + x2’ x4’

10. Mixed-Mode Column-Matching
Simulate first n LFSR patterns
Determine undetected faults
Compute a test for them (ATPG)
Design the Decoder producing test from LFSR patterns > n

11. Mixed-Mode Column-Matching
Example

12. Mixed-Mode Column-Matching
Example

13. Experimental Results Column-matching Bit-fixing Row-matching Bench TL
GEs
c880
1 K
10.5 27 21
c1355
2 K 15
3 K 11
c1908
7.5
4 K 12
4.5 K 8
c2670
5 K
172
121
119
c3540 13 4
c7552
8 K
586
10 K
186
297
s420
24.5 28 -
s641 6
s713
16.5
s838
6 K
130 37
s1196 36

14. Experimental Results Bench inps 100% FC TL (PR + Det.) M DM Overhead
Time [s]
c2670
233
2.4 M
1 K + 1 K
193
173
19 %
166
c7552
207
> 100 M
7 K + 1 K
131 33
500
s420 34
165 K
3 K + 1 K 35 21
11 %
0.41
s641 54
200 K 44
6 %
0.21
s713
300 K 42
5 %
0.32
s838 67 37 13
32 %
26.20
s1196 32
9 K + 1 K 28
1 %
0.04
s5378
214
80 K
20 K + 1 K
205
0.98
s9234
247
10 M
50 K + 1 K
208
138
8 %
350 s
700
100 K
10 K + 1 K
696
137 s
611
> 10 M
478
346
9 %
812
s38417
1664
100 K + 2 K
1503
834
17 K s
1464
> 1 G
100 K + 1 K
1354
b07 50
0.5
b12
126
5 M
118
104
7 % 25
b14
277
100 M / 1 K 90 58
56 %
b15
485
1 M / 2 K
263
158
44 %
65 K

15. What Has Not Been Said Here Yet
Well, there were more problems that had to be solved:
How to choose the lengths of the phases
How to improve the fault coverage in the pseudo-random phase
How to generate test vectors. Or better - what vectors to generate
How to choose the columns to be matched
How to find out if a particular column match is possible to be done
How to synthesize the Decoder logic

16. How to choose the lengths of the phases
Some trade-off has to be found
The PR-phase length influences fault coverage achieved  number of undetected faults  number of deterministic vectors to be generated
The Deterministic phase length influences the design time and BIST area overhead
Fišer, P. - Kubátová, H.: Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST, Proc. 9th Biennial Baltic Electronics Conference (BEC'04), Tallinn (Estonia), , pp

17. How to improve the fault coverage in the pseudo-random phase
What LFSR polynomial and seed to choose?
Or a CA?
Or to modify the patterns somehow?
Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Effect of the Generator Type, ECI'04, Herľany, SR, , pp
Fišer, P. - Kubátová, H.: Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST, Proc. 31th Euromicro Symposium on Digital Systems Design (DSD'05), Porto, (Portugal), , pp
Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Effect of the Generator Type, Acta Polytechnica, Vol. 2, August 2005, CVUT, ISSN , pp

18. How to generate test vectors. Or better - what vectors to generate
It’s better to generate deterministic vectors having many don’t cares
And moreover – we can improve the result by generating more vectors per one fault. It costs time, but the area overhead is smaller
Well, it’s already done, there are positive results, but no publication yet.

19. How to choose the columns to be matched
NP-hard
Heuristic methods have to be used
Fast-search and Thorough-search methods proposed
Fišer, P. - Kubátová, H.: Survey of the Algorithms in the Column-Matching BIST Method, Proc. 10th International On-Line Testing Symposium 2004 (IOLTS'04), Madeira, Portugal, , pp. 181

20. How to find out if a particular column match is possible to be done
NP-C, if don’t cares are present in the test
B-Matrix based approach
Fišer, P. - Hlavička, J. - Kubátová, H.: Column-Matching BIST Exploiting Test Don't-Cares. Proc. 8th IEEE Europian Test Workshop (ETW'03), Maastricht (The Netherlands), , pp

21. How to synthesize the Decoder logic
Two-level Boolean minimizer required
BOOM, FC-Min, BOOM-II developed
Hlavička, J. - Fišer, P.: BOOM - a Heuristic Boolean Minimizer. Proc. International Conference on Computer-Aided Design ICCAD 2001, San Jose, California (USA), , pp
Fišer, P. - Hlavička, J. - Kubátová, H.: FC-Min: A Fast Multi-Output Boolean Minimizer, Proc. 29th Euromicro Symposium on Digital Systems Design (DSD'03), Antalya (TR), , pp
Fišer, P. - Hlavička, J.: BOOM - A Heuristic Boolean Minimizer, Computers and Informatics, Vol. 22, 2003, No. 1, pp
Fišer, P. - Kubátová, H.: Two-Level Boolean Minimizer BOOM-II, Proc. 6th Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany, , pp
… and more

22. Conclusions
Column-matching-based mixed-mode BIST method has been presented
Pseudo-random LFSR patterns are being transformed into deterministic vectors generated by ATPG by the Decoder
We try to match as many of the Decoder outputs as possible with its inputs, which yields no logic necessary to implement these outputs
Mixed-mode – two disjoint BIST phases introduced
Many more “minor” problems involved

23. What Could Be Done Yet Adjust the width of a PRPG
More sophisticated methods should be found, to find a proper PRPG
Incorporate the ATPG into the design process – iterative test computation
Test-per-scan support
Partitioning of the CUT
Combine CM-BIST with other methods