1. Scintillator HCal Prototype
Vishnu V. Zutshi
for the Tile-Cal Group

2. Tile-Cal Group Prague LAL DESY, Hamburg Univ. ITEP, JINR, LPI, MEPhI
Imperial
NIU
5/4/2019
V. Zutshi, Snowmass 2005

3. Prototype ~ 1m3 (38 layers) 2cm (1.6 + 0.2 +0.2) steel absorber
5mm thick scintillator with WLS fiber and SiPM on-board
Aiming at technology and physics goals…..
5/4/2019
V. Zutshi, Snowmass 2005

4. Component schematic FEE Calibration electronics To DAQ Tiles+SiPMs
5/4/2019
V. Zutshi, Snowmass 2005

5. Prototype Geometry Studies
5/4/2019
V. Zutshi, Snowmass 2005

6. Scintillator tiles 12cm x 12cm 3x3 6x6 12 x 12 6cm x 6cm 3cm x 3cm
Tile size
3x3
6x6
12 x 12
need
3500
4000
1000
molded
milled
3000
800
6cm x 6cm
3cm x 3cm
5/4/2019
V. Zutshi, Snowmass 2005

7. SiPM ~1000 pixels on 1mm x 1mm Bias voltage ~ 50-60V Gain ~ 106
Quantum x geom ~ 12-15%
5/4/2019
V. Zutshi, Snowmass 2005

8. ‘Minical’ test 0.5 cm active 2 cm steel
Confidence in SiPM as a calorimetric device
5/4/2019
V. Zutshi, Snowmass 2005

9. SiPM QC Gain, dark rate, cross-talk, saturation monitored to select
SiPM’s for use in HCal.
2500 in hand. Hope to have every
tile instrumented by early 2006
5/4/2019
V. Zutshi, Snowmass 2005

10. Light yield SiPM HV set to Obtain 14-15pe/mip 5/4/2019
V. Zutshi, Snowmass 2005

11. Cassette Commissioning in the e- TB initiated
2 assembled, 4 in the works
5/4/2019
V. Zutshi, Snowmass 2005

12. Cabling
5/4/2019
V. Zutshi, Snowmass 2005

13. Base board Charge Injection Dimensions: 16 x 16 cm²
2 base boards (12
amplifier cards) / layer
SiPM Interface, 18 chns.
Charge Injection
Test Outputs (SRIN, TCALIB)
DAQ Interface
Dimensions:
16 x 16 cm²
HAB
5/4/2019
V. Zutshi, Snowmass 2005

14. Front-end ASIC ASIC 8-bit DAC 1-5V in
100nF
10pF
Variable Gain Charge Preamplifier
Variable Shaper CR-RC²
12kΩ
4kΩ
24pF
12pF
3pF in
8pF
4pF
2pF
1pF
40kΩ
8-bit
DAC
1-5V
ASIC
5kΩ
50Ω
100MΩ
2.4pF
1.2pF
0.6pF
0.3pF
0.1pF
0.2pF
0.4pF
0.8pF
6pF
Test_pulse
5/4/2019
V. Zutshi, Snowmass 2005

15. Amplifier Board Parameter Shift-Reg Temperature Monitor ASIC
ASIC’s all tested. Boards being
assembled.
Analog Line Driver
5/4/2019
V. Zutshi, Snowmass 2005

16. Data Acquisition Use modified version of the
ECal (CERC) board. Similar no.
of analog channels.
8x12 (16-bit) ADC’s
8Mb memory (2k events)
1 KHz peak rate
180ns trigger latency
Have been used successfully
In ECal test beam run
Become available in Nov.
5/4/2019
V. Zutshi, Snowmass 2005

17. Calibration & Monitoring
Observation of single pe for
non-linearity correction.
Need mip and variable
Intensity LED calibration
Gain  1.7% / K , 2.5% / 0.1V
Signal Amplitude  4.5% / K , 7% / 0.1V
5/4/2019
V. Zutshi, Snowmass 2005

18. CAN (ADC, Enable Pulser, DAC)
Monitoring
CMB T
CAN (ADC, Enable Pulser, DAC)
Gadow
Goettlicher, Reinecke
HBAB_TOP
HBAB_BOT
Redundant monitoring:
Reference LED pulse
Direct gain monitoring
temperature and
voltage monitoring
5/4/2019
V. Zutshi, Snowmass 2005

19. Absorber stack and table
Layer 1
Construction of moveable
table in spring 2006
Will be used for all CALICE
HCal options.
5/4/2019
V. Zutshi, Snowmass 2005

20. Summary Tail Catcher Electronic Racks HCAL ECAL Beam
Preparing for test beam in summer-fall of 2006
5/4/2019
V. Zutshi, Snowmass 2005