1. EE4271 VLSI Design Advanced Interconnect Optimizations Buffer Insertion

2. Objectives What have we learned? What are we going to learn?
Buffer insertion on a single wire
What are we going to learn?
Buffer insertion on a tree

3. Timing Driven Buffering Problem Formulation
Given
A Steiner tree
RAT at each sink
A buffer type
RC parameters
Candidate buffer locations
Find buffer insertion solution such that the slack at the driver is maximized

4. Candidate Buffering Solutions

5. Candidate Solution Characteristics
Each candidate solution is associated with
vi: a node
ci: downstream capacitance
qi: RAT
vi is a sink
ci is sink capacitance
v is an internal node

6. Van Ginneken’s Algorithm
Candidate solutions are propagated toward the source

7. Solution Propagation: Add Wirex
(v1, c1, q1)
(v2, c2, q2)
c2 = c1 + cx
q2 = q1 – rcx2/2 – rxc1
r: wire resistance per unit length
c: wire capacitance per unit length

8. Solution Propagation: Insert Buffer
(v1, c1, q1)
(v1, c1b, q1b)
c1b = Cb
q1b = q1 – Rbc1
Cb: buffer input capacitance
Rb: buffer output resistance

9. Solution Propagation: Merge
(v, cl , ql)
(v, cr , qr)
cmerge = cl + cr
qmerge = min(ql , qr)

10. Solution Propagation: Add Driver
(v0, c0, q0)
(v0, c0d, q0d)
q0d = q0 – Rdc0 = slackmin
Rd: driver resistance
Pick solution with max slackmin

11. Example of Merging
Left candidates
Right candidates
Merged candidates

12. Solution Pruning Two candidate solutions Solution 1 is inferior if
(v, c1, q1)
(v, c2, q2)
Solution 1 is inferior if
c1 ≥ c2 : larger load
and q1 ≤ q2 : tighter timing

13. Merging Branches
Right
Candidates
Left

14. Pruning Merged Branches
Critical
With pruning

15. Exercise (5,10) (8,15) (10,20) (12,25) (2,7) (7,10) (9,15)
Compute candidate buffer solutions after merge.

16. Exercise (20,400) 2 2 2 2 (15,300) Unit Wire Cap = 5 Unit Wire Res = 3
Buffer C=5, R=1
Perform buffer insertion to maximize the slack at driver

17. Summary Buffer insertion on a tree
Solution pruning can significantly reduce the number of solutions