1. ECE 352 Digital System Fundamentals
Introduction to Memory
In this presentation, we will look the fundamental concepts of memory devices.

2. Random Access Memory (RAM)
Information stored as groups of bits (words)
A group of 8 bits is a “byte”
A group of 4 bits is a “nibble” (or “nybble”)…
The capacity of a memory is the total number of bits it can store
Also stated numwords x wordsize (depth x width)
The SI prefixes (K, M, G, T, P) are used, BUT…
K = 210, M = 220, G = 230, T = 240, P = 250
A kilobyte is 1024 bytes, not 1000 bytes!
Note that this can be confusing and lead to errors
Communications systems typically use the actual SI prefix meanings, so a 1 kb/s communication link can only transmit 1,000 bits per second, not 1,024 bits per second!
See
In a memory, a data element is stored as a group of bits. We commonly refer to a group of 8 bits as a byte, and a group of 4 bits as a nibble. The total number of bits that a memory can store is its capacity. We often also state a memory’s capacity in terms of its depth (the number of words it can store) and its width (the number of bits in each word). Since memories store many bits, we use the SI prefix names such as kilo and mega to state large numbers succinctly. However, we use these prefixes in a nonstandard way. Instead of being powers of ten, the prefixes represent powers of two. For example, a kilobyte is 2^10 bytes, not 10^3 bytes. This can be confusing, especially when working across disciplines. Communications systems typically use the true SI prefixes, so a 1 kilobit per second communications link cannot send the contents of a 1kb memory (1,024 bits) in one second. You’ll want to aware of this issue in your professional practice. An alternate standard for binary prefixes was created to try to avoid confusion, but this never really caught on. You can follow this link for further information.

3. A Logical Model of Memory
An m x n memory is similar (logically) to a register file with m registers, each n bits in size
Locations accessed using a k-bit address (m ≤ 2k)
Reading: chooses which “register” value appears at output
Writing: chooses which “register” to enable
Data is transferred on an n-bit input port (for writes) and an n-bit output port (for reads)
Or a single n-bit bidirectional data port
Control signals indicate if it should read or write
May have separate read and write signals, or a single R/ W signal (read when 1, write when 0)
May include a “chip select” that acts as an enable on both the read and write operations (DOUT must be tristated…)
Logically, we can view memory as an array of registers, like a large register file. We select the location to access by applying an address to the memory. If we are reading, the address controls which location provides the output data. When writing, the address determines which location will be updated. The memory devices we will look at have data input and output ports that are as wide as the memory word size so we can transfer a whole word at once. However, in some devices, the input and output data are combined onto a single bidirectional port. There are also memories that use a serial interface, but we aren’t going to discuss these. The memory needs to have control signals that tell it when to read or write. One possibility is to have two control signals; one to tell it when to read and one to tell it when to write. More commonly, there is one signal that enables the memory device, called a chip select, and another signal to tell it which operation to perform while it is enabled. Most memory devices use tristate drivers on the data outputs, to permit multiple memories to be connected directly to a data bus.

4. Example Memory Symbol # of words (m ≤ 2k) word size
indicates DOUT not driven if CS = 0
data input
address
Here’s an example symbol for an m-by-n SRAM. It has a separate data input and data output, which we use to write to and read from the memory. The size of these buses is equal to the word size, which is n. The address input lets us control which location we read from or write to. The address size is related to the number of words in the memory, since a k-bit address can differentiate between up to 2^k locations. Remember, each location stores one word of data. This memory has a single signal to control whether it reads or writes. This notation indicates that if the read/not-write signal is 1, the memory performs a read, and if it is 0, the memory performs a write. Finally, there is a chip select signal, which is a global enable for the memory device. The triangle above the output port name indicates that the output is not driven if the chip is not enabled. This will be particularly important later when we combine multiple devices to create larger memory arrays.
data output
chip select
read/write

5. Example Memory Symbol 8K × 16 SRAM
8192 words, each of which is 16 bits wide
# of words
word size
8K ×
16 SRAM 16
# address bits 13
= log2(8K) 16
= log2(213)
Let’s look at a more specific example of how we would label an SRAM that can store just over 8 thousand words, each of which is 16 bits wide. Remember, 8192 words equals 8K words. To uniquely identify each one of the 8K words, we need 13 address bits. We know the size of each word is 16 bits, which is also the size of the Din and Dout buses. We can also determine the total capacity of this memory by multiplying the number of locations by the size of each location. Remember, 1K is 2^10. After doing the math, we see the capacity is 128K bits. We know 2^17 is 128K because 128 is 2^7 and 1K is 2^10.
= 13
27 × 210
Total capacity = 8K×16
= (8×210)×16
= 23 ×210 × 24
= 217
= 128K bits

6. R/ W = 1 the whole time to avoid writing
Read From Memory
Apply desired address
Enable memory and activate read signal
Some designs: memory continually reads
Other designs: memory continually reads when not writing…
Data driven onto DOUT port after some time
Often more than one processor cycle
memory access time
To perform a read operation, we first apply the address of the desired location. We enable the memory by asserting its chip select signal, and set the read/not-write line to 1, indicating a read operation. In fact, we keep the read/not-write line 1 the entire time to avoid writing. In some memory designs, the output data is continuously driven with the content of the addressed location, and others may do a read operation whenever they are not being written to. After some time, the data from the location becomes available on the memory’s data output. This is often a relatively long delay compared to a typical processor’s cycle time. The time from when the address is applied until the data becomes valid is referred to as the memory access time. This is a key memory performance parameter.
R/ W = 1 the whole time to avoid writing

7. memory write cycle time
Write To Memory
Apply desired address and enable memory
Apply data to the data input and activate write signal
After data has been written, deactivate write signal
After that, the data/address are allowed to change and can disable memory
Must avoid writing incorrect data and/or to incorrect location!
memory write cycle time
When writing to memory, we apply the address and assert the chip select. Then, we apply the data to be stored, and set the read/not-write line to 0 to signal the memory that it should store the input data to the indicated address. We hold the signal values for the length of time required by the memory to perform a write. Then we stop signaling a write, before disabling the memory or changing the address or data. When doing a write, we need to carefully control the sequence of signals to prevent writing to any other location, and to ensure that the data is correctly stored. The minimum time to perform a write operation is the memory write cycle time. Note that real memory devices have very detailed and complex timing requirements – much more complex than what we’ve shown here. So you will need to consult the datasheet for a given memory to determine the exact sequence and timing of the signals used to perform an operation.

8. Memory Cells
There are two different storage mechanisms used to hold a single bit in RAM devices
Static RAM (SRAM)
Dynamic RAM (DRAM)
Each bit stored in a latch or flip-flop
As long as power is applied, data is held
Each bit stored as a charge in a capacitor
Leaks charge over time
Value must be periodically refreshed by reading it back, then re-writing it
All bits in a given memory are stored using the same type of structure. However, there are two different types of these structures.
In a static RAM, or SRAM for short, each bit of data is held in a latch, such as the D latch shown here. Instead of a tristate buffer, this structure is controlled by a pass transistor, which is smaller. As long as the device is powered, the latch will hold its value. In a dynamic RAM, or DRAM for short, the data is stored as an electric charge in a microscopic capacitor. This makes the DRAM cell very small, so we can build DRAMs with very high capacities. Unfortunately, the very tiny capacitor and the transistor connected to it aren’t perfect, so charge will leak out of it (or into it) over time, and the stored value will be lost. To avoid losing the stored value, every few milliseconds we must read each DRAM cell and write its value back to it to restore the capacitor to the correct amount of charge. We refer to this process as a “refresh” operation.

9. DRAM Devices More complicated than SRAM, but also smaller
Has more capacity within a given area (cheaper!)
Due to their large capacity, DRAMs typically use multiplexed addressing
Conceptually “rearrange” memory into a 2D grid…
Instead of using a single large address, use separate row and column addresses to identify a word
Send each part of the address separately to the DRAM
Row/column addresses are held in registers in the DRAM device & used together to access memory word
This makes DRAM addressing more complex!
Although dynamic RAM devices have the added complexity of requiring a periodic refresh, they are used as the main memory system in nearly all computers. Because of the very small capacitor used for storage, we can fit many more bits per unit area than we can with static memory, so we can create very high capacity memory devices. The high capacity, however, also means DRAM addresses typically have very large bitwidths. DRAM devices typically split the address in half, and then use a single half-size address bus to send each part separately, a process called multiplexing. This reduces the number of pins on the devices and the number of interconnections. Inside the DRAM, the row and column parts of the address are stored in registers, and the full address is then used to access the desired word in the array of memory cells. This makes DRAM addressing much more complex than static RAM devices. In the remaining videos, we will focus on SRAM devices, but you should be aware that DRAM is an absolutely critical technology to the modern computer. If you install memory in a computer – chances are that you’re installing dynamic memory!

10. Memory Properties & Terminology
Memory may be static or dynamic
Refers to the design of the memory cell (shown earlier)
Volatile memory loses its contents when power is removed
Includes both static and dynamic memory
Nonvolatile memory retains information when power is removed (flash, optical, magnetic, etc.)
Memory devices can be classified in a number of ways. We’ve just discussed static versus dynamic, which refers to the design of the memory cell itself. We can also classify memories by their volatility. A volatile memory is one that loses its contents when power is removed. The static and dynamic memory technologies we looked at are both volatile. A nonvolatile memory is one that retains its data even when power is removed. You are probably familiar with a number of these technologies, including magnetic disks and flash memory in computer data drives, and optical storage in the case of CDs and DVDs. There are a number of other emerging technologies that may be used for nonvolatile storage in the future.

11. Memory Properties & Terminology
Some commonly-used memory terms are misnomers!
Random Access Memory (RAM)
Requires same amount of time to access any location
What would a sequential-access memory look like?
We use this name to mean we can read and write during normal operation
Read Only Memory (ROM)
Can only read during normal operation
We use this to mean a non-volatile memory
Two of the most familiar and common memory-related terms are actually technically incorrect. A random-access memory, or RAM, is one where the time to access a location is the same regardless of the address of the location. An alternative is a sequential-access memory. Think about an audio, video, or data backup tape. You cannot directly access an arbitrary location. Instead you must go to the desired location by traveling, from the current location, through every other location along the way until you get there. In practice, we use RAM to mean a memory that we can both read from and write to in normal operation. The term ROM, or read-only memory, refers to a memory device that can be read from during normal operations, but cannot be written to except by some type of programming device, typically at the factory. In practice, the term ROM is often used to describe the non-volatile memory in a system.

12. ECE 352 Digital System Fundamentals
Introduction to Memory
This concludes our introduction to memory concepts. In the next videos, we’ll look at memory devices and systems in more detail.