1. Innovative Sequential Synthesis and Verification
Logic Synthesis and Verification Group
Department of EECS
UC Berkeley
Robert Brayton
Mike Case
Satrajit Chatterjee
Sungmin Cho
Aaron Hurst
Alan Mishchenko
Zile Wei

2. Overview Introduction Innovations in synthesis and verification
Overview of current R&D activities
Recent publications
Future work
Conclusions

3. Introduction Research goals
researching solutions for a variety of EDA problems
producing algorithms that are competitive in quality but faster than the currently used ones
developing new efficient implementations and releasing the source code to the community

4. Innovations Synthesis Verification
from SOP/BDD logic representations ― to AIGs and truth tables
from combinational ― to “sequentially transparent”
from one-snapshot ― to multiple-snapshot synthesis
from separated ― to integrated (synthesis/mapping/retiming)
from complex and slow algorithms ― to simple and fast
AIG rewriting vs. traditional synthesis flows
priority-cut-based mapping vs. traditional cut-based mapping
Verification
from predominantly combinational ― to sequential
from trusted ― to independently verifiable using certificates
from separate ― to synergistically combined with synthesis
using fast synthesis as a preprocessing/intermediate step
using synthesis information to speed up verification

5. Overview of Current Activities
Current research directions
Logic synthesis based on AIGs
Improvements to AIG rewriting
FPGA mapping using priority cuts
Integrated synthesis/mapping/retiming
Fast retiming algorithms
Co-developing synthesis and verification
Developing new implementations in ABC
ABC is a growing logic synthesis and verification system
It reflects the current state of our research findings
It is increasingly adopted in academia and industry

6. AIG-Based Logic Synthesis
Logic representation
Traditional: Logic network with SOPs/BDDs stored at each node
Innovative: AIG (And-Inverter Graph)
AIG representation has several advantages
Faster, more scalable, leads to algorithms searching a larger space of solutions
AIG rewriting revolutionizes logic synthesis
Consider function f = abc
Rewriting node A a b c A
Subgraph 1 b c a A
Subgraph 2 a b c
Subgraph 1 b c a
Subgraph 2 a c b
Subgraph 3 
Rewriting node B b c a B
Subgraph 2 a b c B
Subgraph 1  a b c

7. Why AIG Rewriting is Efficient?
Using all K-feasible cuts explores all fanin-limited node boundaries
Traditional synthesis is limited to only one node boundary
Using all fanin-limited Boolean divisors
Traditional synthesis is limited to algebraic kernels extracted from the current SOPs of the nodes
AIG-based synthesis uses all sequential cuts
Traditional sequential synthesis is limited to retiming
Iterating fast local transforms many times
Traditional synthesis is often too slow to allow multiple iterations
Experimental results can be found in DAC 2006 paper

8. FPGA Mapping using Priority Cuts
Traditional mapping
computes all cuts, finds optimum-depth cut, iterates area recovery
runtime/memory are dominated by cut computation and evaluation
Mapping based on priority cuts
computes a small number (typically, 4-8) good cuts at each node
achieves near-optimum depth; performs iterations of area recovery
reduces runtime/memory requirements (5x for K = 6; 25x for K = 8)
holds promise for sequential mapping k
Average number of cuts per node 4 6 5 20 80 7
150 8
350 n p k a b s c
PIs: a, b, c
3-feasible cuts of n:
C1 = { p, k }
C2 = { a, b, s }
Not 3-feasible cuts of n:
C3 = { p, b, c }
C4 = { a, b, s, c }

9. Recent Work on Retiming
Implemented three flavors of retiming:
Delay-oriented retiming based on iterative sequential arrival time computation [P. Pan, ICCD ’97 and FPGA ‘98]
Often increases the number of registers considerably (50-100%)
Incremental heuristic delay-oriented retiming [D. P. Singh, DAC ’05]
The register increase is better controllable but still possible
New minimum-register retiming based a simplified version of maximum-flow [submitted to DAC ’07]
Minimizes the number of registers but ignored the delay
Need a hybrid approach that is
Fast and scalable
Doing a good job on both delay and register count
Another possibility is to combine retiming and clock skewing
Start with minimum-register retiming
Find a trade-off between retiming and skewing, which takes into account
The cost of additional registers due to partial retiming
The cost of additional buffers due to partial skewing
Studying new promising delay-optimal algorithm [H. Zhou, ASPDAC ’05]

10. Integrated Mapping and Retiming
A year ago, developed an integrated solution for minimizing delay while performing synthesis/mapping/retiming
The approach suffers from area penalty
Currently working on a second-generation solution
Uses priority cuts
Reduces mapping/retiming to combinational mapping while guaranteeing delay optimality in almost all cases
Promising results
Delay improvement ~28% (compared to 4-19% for retiming alone)
Area is comparable to area after combinational mapping
Faster and more scalable due to using priority cuts

11. Verification Capabilities
Combinational equivalence checking (ICCAD 2006)
developed an AIG package with functional reduction (“SAT sweeping”)
developed a CEC engine based on AIGs, simulation, and SAT
successfully used them in several academic and industrial projects
Incremental verification after synthesis (IWLS 2006)
uses synthesis information stored in the form of a history AIG
verification runtime does not exceed synthesis runtime
scalable verification is a consequence of scalable synthesis
General purpose sequential equivalence checking (work in progress)
will leverage the strengths of the robust CEC engine
will be based on a synergistic combination of induction and interpolation
may benefit greatly from fast logic synthesis as a pro-processor
Recording verification certificates and verifying them (accepted to DAC ’07)
Producing extended resolution proofs of each step in verification
Composing individual proofs into one final proof
Independently verifying this proof using a very simple resolution checker
Synthesis and verification are two sides of the same coin

12. ABC: Logic Synthesis and Verification System
Public-domain source code and manuals:
New release will be out in about a week
Variety of input formats (BLIF, BENCH, AIGER)
recently added: hierarchical BLIF, hierarchical Verilog (structural netlist)
Improved AIG rewriting package
Improved FPGA mapper
Improved CEC engine
New retiming engine (min-register, min-delay, etc)
Experimental code for sequential rewriting and choice accumulation
Designed to handle very large designs

13. Recent Publications Combinational AIG rewriting
A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC '06, pp
Synthesis/mapping/retiming combined
A. Mishchenko, S. Chatterjee, R. K. Brayton, and P. Pan, "Integrating logic synthesis, technology mapping, and retiming", ERL Technical Report, UC Berkeley, April '06.
Improved LUT-mapping based on cut enumeration
A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for LUT-based FPGAs". IEEE TCAD, Vol. 26(2), Feb 2007, pp
Combinational equivalence checking
A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een, "Improvements to combinational equivalence checking", Proc. ICCAD '06.
Verifying verification tools
S. Chatterjee, A. Mishchenko, R. Brayton, and A. Kuehlmann, "On resolution proofs for combinational equivalence checking", Accepted to DAC ‘07.

14. Papers Submitted to IWLS
Integrating logic synthesis and placement
Optimum placement of non-reconvergent DAGs by dynamic programming
Logic optimization and mapping
Mapping with priority cuts
SAT-based logic optimization and re-synthisis
Sequential rewriting
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Benchmarking logic synthesis for FPGAs
Retiming
Fast minimum-register retiming via binary maximum-flow
Minimizing implementation costs with end-to-end retiming
Model checking
Automated extraction of inductive invariants to aid model checking

15. Ongoing and Future Work
Synthesis
Placement-aware AIG-based synthesis and technology mapping
Integrated synthesis/mapping/retiming using priority cuts
AIG optimizations with don’t-cares and Boolean decomposition
Verification
Developing a verification system with information from synthesis
Developing a new sequential equivalence checking package
Recording resolution proofs of CEC and SEC
Releasing updated versions of ABC

16. Conclusions Reviewed current state of our research
Logic synthesis based on AIGs
Improvements to AIG rewriting
LUT mapping using priority cuts
Integrated synthesis/mapping/retiming
Fast retiming capabilities
Bridging the gap between synthesis and verification
Listed recent publications
Outlined future work