1. NTU DSD (Digital System Design) 2007
Boolean Algebra
2019/5/1
NTU DSD (Digital System Design) 2007

2. NOT Operation
The NOT operation (or inverse, or complement operation) replaces a Boolean value with its complement:
0’ = 1
1’ = 0
A’ is read as NOT A or Complement A
Boolean representation F(A) = A’ = A
Truth Table A A’ A A’ 1 1
Inverter symbol
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Jackie Kan

3. AND Operation The AND operation is a function of two variables (A, B)
Boolean function representation F(A,B) = A • B = A * B = AB
When both A and B are ‘1’, then F is ‘1’ • 0 = • 1 = • 0 = • 1 = 1
Truth Table A B Y A Y 1 1 B 1 1 1
and symbol
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Jackie Kan

4. OR Operation The OR operation is a function of two variables (A, B) A
Boolean function representation F(A,B) = A + B
When either A or B are ‘1’, then F is ‘1’ = = = = 1
Truth Table A B Y A Y 1 1 1 1 B 1 1 1
or symbol
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Jackie Kan

5. XOR Operation
XOR gate is usual in logic circuits that do binary addition/subtraction.
Note that:
F = A  B = A’B + AB’ A B Y 1 1 1 1 1 1
Y=A  B A B
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Jackie Kan

6. Boolean Functions
More complex Boolean functions can be created by combining basic operations A A’
F(A,B) = A’ + B B A B A’
F(A,B) = A’ + B 1 1 1 1 1 1 1 1 1
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Jackie Kan

7. 7408 – Quad 2-Input AND Gate IC
7432 – Quad 2-Input OR Gate IC
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8. 7404 – Hex Inverter 7486 – Quad 2-Input Exclusive-OR Gate IC 2019/5/1
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9. Laws and Theorems of Boolean Algebra
單變數定理(Single Variables Theorem)
Identity
X + 0 = X
X * 1 = X
Null Element
X + 1 = 1
X * 0 = 0
Idempotent Theorem
X + X = X
X * X = X
Theorem of Complementarity
X + X’ = 1
X * X’ = 0
Involution Theorem
(X’)’ = X
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Jackie Kan

10. Laws and Theorems of Boolean Algebra
多變數定理(Multiple Variables Theorem)
Commutative law
X + Y = Y + X
XY = YX
Associative law
(X + Y) + Z = X + (Y + Z) = X + Y + Z
(XY)Z = X(YZ) = XYZ
Distributive law
X(Y + Z) = XY + XZ
X + (YZ) = (X + Y)(X + Z)
Simplification theorems
XY + XY’ = X (uniting)
X + XY = X (absorption)
(X + Y’)Y = XY
(X + Y)(X + Y’) = X
X(X + Y) = X
XY’ + Y = X + Y
Consensus theorem
XY + X’Z + YZ = XY + X’Z
(X + Y)(X’ + Z)(Y + Z) = (X + Y)(X’ + Z)
2019/5/1
Jackie Kan

11. Proof of The Consensus Theorem
XY + X’Z + YZ = XY + X’Z
XY + X’Z + YZ = XY + X’Z + 1·YZ = XY + X’Z + (X + X’)YZ = XY + X’Z + XYZ + X’YZ = XY + XYZ + X’Z + X’YZ = XY(1 + Z) + X’Z(1 + Y) = XY·1 + X’Z·1 = XY + X’Z
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Jackie Kan

12. Boolean Algebra and Truth Table
利用真值表證明兩邊的式子
範例：
證明 x•(y + z) = (x • y) + (x • z) x y z
y + z
x •(y + z)
x •y
x •z
(x • y) + (x•z) 1
x(y + z) = xy + xz
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Jackie Kan

13. Simplification / Minimization (簡化)
Simplification or Minimization tries to reduce the number of terms in a Boolean equation via use of basic theorems
A simpler equation will mean:
Less gates will be needed to implement the equation
Could possibly mean a faster gate-level implementation
Will use algebraic techniques at first for simplification
Graphical method called K-maps
Computer methods for simplification are widely used in industry
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Jackie Kan

14. Minimization Example Example: full adder's carry out function
Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin = A' B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin = (A' + A) B Cin + A B' Cin + A B Cin' + A B Cin = (1) B Cin + A B' Cin + A B Cin' + A B Cin = B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin = B Cin + A (B' + B) Cin + A B Cin' + A B Cin = B Cin + A (1) Cin + A B Cin' + A B Cin = B Cin + A Cin + A B (Cin' + Cin) = B Cin + A Cin + A B (1) = B Cin + A Cin + A B
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Jackie Kan

15. Computation in Digital Logic Circuit
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NTU DSD (Digital System Design) 2007

16. Half Adder / Full Adder S = A’B + AB’ Cout = AB Full Adder 2019/5/1
Jackie Kan

17. Full Adder with Truth TableS
= A’B’Cin + A’BCin’ + ABCin + AB’Cin’
= A’(B’Cin + BCin’) + A(B’Cin’ + BCin)
= A’(B ⊕ C) + A(B ⊕ C)’
= A⊕(B⊕Cin)
= (A⊕B)⊕Cin
Cout
= A’BCin + AB’Cin + ABCin’ + ABCin
= BCin + ACin + AB
F = A  B = A’B + AB’
2019/5/1
Jackie Kan

18. Circuit of Full Adder S = A⊕B⊕Cin = (A⊕ Cin)⊕B Cout = AB + BCin + ACin
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Jackie Kan

19. Behavior Level of Full Adder in Verilog Code
module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co;
assign s = a ^ b ^ ci;
assign co = (a & b) | (a & ci) | (b & ci);
endmodule
Gate Level of Full Adder in Verilog & VHDL Code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY full_add IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END full_add;
ARCHITECTURE behv OF full_add IS
BEGIN
sum <= a XOR b XOR c_in;
c_out <= (a AND b) OR (c_in AND (a OR b));
END behv;
module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co;
wire NET1, NET2, NET3, NET4 ;
xor ( NET1, a, b );
xor ( s , NET1, ci );
and ( NET2, a, b );
and ( NET3, a, ci );
and ( NET4, b, ci );
or ( co, NET2, NET3, NET4 );
endmodule
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Jackie Kan

20. Verilog Code of 4-Bit Adder
module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co;
assign s = a ^ b ^ ci;
assign co = (a & b) | (a & ci) | (b & ci);
endmodule
module f_fadder (a, b, s, co);
input [3:0] a;
input [3:0] b;
output [3:0] s;
output co;
wire net1, net2, net3;
full_adder f1(a[0],b[0],0,s[0],net1);
full_adder f2(a[1],b[1],net1,s[1],net2);
full_adder f3(a[2],b[2],net2,s[2],net3);
full_adder f4(a[3],b[3],net3,s[3],co);
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Jackie Kan

21. Answer of Quiz 1 1) Please complete this truth table X Y Z XY Y’+Z’
XZ’
X’Y + XZ’ 1
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22. Answer of Quiz 2
2) Please design an 8-bit adder by drawing block diagram, schematic and related Verilog code
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Jackie Kan 22

23. Answer of Quiz 2 module full_adder (a, b, ci, s, co); input a, b, ci;
output s, co;
assign s = a ^ b ^ ci;
assign co = (a & b) | (a & ci) | (b & ci);
endmodule
module f_fadder (a, b, s, co);
input [7:0] a;
input [7:0] b;
output [7:0] s;
output co;
wire net1, net2, net3, net4, net5, net6, net7;
full_adder f1(a[0],b[0],0,s[0],net1);
full_adder f2(a[1],b[1],net1,s[1],net2);
full_adder f3(a[2],b[2],net2,s[2],net3);
full_adder f4(a[3],b[3],net3,s[3],net4);
full_adder f5(a[4],b[4],net4,s[4],net5);
full_adder f6(a[5],b[5],net5,s[5],net6);
full_adder f7(a[6],b[6],net6,s[6],net7);
full_adder f8(a[7],b[7],net7,s[7],co);
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24. Basic Input / Output Device
Input Devices
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NTU DSD (Digital System Design) 2007

25. Logic Switch Circuit Logic Levels 1 Open Closed Open
High Input Resistance
Logic Levels 1
Open
Closed
Open
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Jackie Kan

26. Normally Open / Closed Pushbutton
Press
Release
Press
Release 1 1
Closed
Open
Closed
Open
Closed
Open
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27. Example 4x4 Keypad
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28. Keyboard Scan 1 1 1 1 1
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29. Keyboard Scan 1 1 1 1
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30. PS/2 Keyboard
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31. Make Code & Break Code 2019/5/1
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32. Button Bounce Analog Waveform Digital Waveform Debounce 2019/5/1
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