1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Counters CprE 281: Digital Logic Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff Homework 8 is out
It is due on Monday Nov 11, 2013

4. Flip-Flops

5. Circuit Diagram for the Gated D Latch
[ Figure 5.7a from the textbook ]

6. Constructing a D Flip-Flop

7. Constructing a D Flip-Flop

8. Constructing a D Flip-Flop (with one less NOT gate)

9. Constructing a D Flip-Flop (with one less NOT gate)

10. Edge-Triggered D Flip-Flops

11. Master-Slave D Flip-FlopQ
Master
Slave
Clock m s
Clk
(a) Circuit
[ Figure 5.9a from the textbook ]

12. Negative-Edge-Triggered Master-Slave D Flip-FlopQ
Master
Slave
Clock m s
Clk
Positive-Edge-Triggered Master-Slave D Flip-Flop D Q
Master
Slave
Clock m s
Clk

13. Registers

14. Register (Definition)
An n-bit structure consisting of flip-flops

15. A simple shift registerD Q
Clock In
Out t 1 2 3 4 5 6 7 =
(b) A sample sequence
(a) Circuit
[ Figure 5.17 from the textbook ]

16. Parallel-access shift register
[ Figure 5.18 from the textbook ]

17. Counters

18. A three-bit up-counter
[ Figure 5.19 from the textbook ]

19. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
[ Figure 5.19 from the textbook ]

20. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
[ Figure 5.19 from the textbook ]

21. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1
[ Figure 5.19 from the textbook ]

22. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

23. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
The propagation delays get longer
[ Figure 5.19 from the textbook ]

24. A three-bit down-counter
[ Figure 5.20 from the textbook ]

25. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
[ Figure 5.20 from the textbook ]

26. Synchronous Counters

27. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

28. A four-bit synchronous up-counter
The propagation delay through all AND gates combined must
not exceed the clock period minus the setup time for the flip-flops
[ Figure 5.21 from the textbook ]

29. A four-bit synchronous up-counterQ
Clock 1 2
(a) Circuit
Count 3 5 9 12 14
(b) Timing diagram 4 6 8 7 10 11 13 15
[ Figure 5.21 from the textbook ]

30. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
[ Table 5.1 from the textbook ]

31. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
T0= 1
T1 = Q0
T2 = Q0 Q1
[ Table 5.1 from the textbook ]

32. A four-bit synchronous up-counter
T1 = Q0
T2 = Q0 Q1
[ Figure 5.21 from the textbook ]

33. In general we have T0= 1 T1 = Q0 T2 = Q0 Q1 T3 = Q0 Q1 Q2 …
Tn = Q0 Q1 Q2 …Qn-1

34. Adding Enable and Clear Capability

35. Inclusion of Enable and Clear capabilityQ
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

36. Inclusion of Enable and Clear capability
This is the new thing relative to
the previous figure, plus the clear_n line T Q
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

37. Figure 5.56. Providing an enable input for a D flip-flop.

38. Synchronous Counter with D Flip-Flops

39. A four-bit counter with D flip-flops
[ Figure 5.23 from the textbook ]

40. Counters with Parallel Load

41. A counter with parallel-load capability
[ Figure 5.24 from the textbook ]

42. A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]

43. Reset Synchronization

44. Motivation An n-bit counter counts from 0, 1, …, 2n-1
For example a 3-bit counter counts up as follow
0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, …
What if we want it to count like this
0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, …
In other words, what is the cycle is not a power of 2?

45. What does this circuit do?
[ Figure 5.25a from the textbook ]

46. A modulo-6 counter with synchronous reset
Enable Q 1 2 D
Load
Clock 3 4 5
Count
(a) Circuit
(b) Timing diagram
[ Figure 5.25 from the textbook ]

47. A modulo-6 counter with asynchronous resetQ
Clock 1 2
(a) Circuit
Count
(b) Timing diagram 3 4 5
[ Figure 5.26 from the textbook ]

48. A modulo-6 counter with asynchronous resetQ
Clock 1 2
(a) Circuit
Count
(b) Timing diagram 3 4 5
The number 5 is displayed
for a very short amount of time
[ Figure 5.26 from the textbook ]

49. Questions?

50. THE END