1. Status of pixel study
2nd CMOS sensor (CPS) submission: digital CPS prototypes design at IHEP & CCNU
In-pixel digitization and readout structure study
May of 2017 (process: TowerJazz CiS 180nm)
Ping Yang’s talk
Rolling shutter mode
Global shutter mode
In-pixel front-end
2 stage single end version
Differential version
Self designed
ALPIDE-like
+Digital processing
Pixel size
22×22 um % ↓vs ASTRAL chip
25×25 um %↓vs ALPIDE chip
Diode Biasing
Positive biased
Negative biased
Sensor size
3 × 3.3 mm2
3.2 × 3.7 mm2
Matrix
96 × 112
128 × 64
CPS test: modified versions of both mother board and daughter board finished
Design of SOI sensor (CPV2)
Pixel size: 16μm×16μm
Digital readout
Thinning to 75μm
Test of SOI sensor (CPV1) in progress
Yunpeng Lu’s talk