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Semiconductor Device Modeling & Characterization Lecture 21

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Presentation on theme: "Semiconductor Device Modeling & Characterization Lecture 21"— Presentation transcript:

1 Semiconductor Device Modeling & Characterization Lecture 21
Professor Ronald L. Carter Spring 2001 L21 April 3

2 Fully biased n-MOS capacitor
VG Channel if VG > VT VS VD EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y L21 April 3 L

3 Flat band with oxide charge (approx. scale)
SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev L21 April 3

4 MOS energy bands at Si surface for n-channel
Fig 8.10** L21 April 3

5 Fully biased n- channel VT calc
L21 April 3

6 Q’d,max and xd,max for biased MOS capacitor
Fig 8.11** |Q’d,max|/q (cm-2) xd,max (microns) L21 April 3

7 n-channel VT for VC = VB = 0
Fig 10.20* L21 April 3

8 Flat-band parameters for p-channel (n-subst)
L21 April 3

9 Fully biased p- channel VT calc
L21 April 3

10 p-channel VT for VC = VB = 0
Fig 10.21* L21 April 3

11 Differential charges for low and high freq
From Fig 10.27* L21 April 3

12 Ideal low-freq C-V relationship
Fig 10.25* L21 April 3

13 Comparison of low and high freq C-V
Fig 10.28* L21 April 3

14 Effect of Q’ss on the C-V relationship
Fig 10.29* L21 April 3

15 Conductance of inverted channel
Q’n = - C’Ox(VGC-VT) n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2) The conductivity sn = (n’s/t) q mn G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’sqmnW) L21 April 3

16 Basic I-V relation for MOS channel
L21 April 3

17 n-channel enhancement MOSFET in ohmic region
0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ e-e- e- e- e- n+ Depl Reg p-substrate Acceptors VB < 0 L21 April 3

18 Conductance of inverted channel
Q’n = - C’Ox(VGC-VT) n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2) The conductivity sn = (n’s/t) q mn G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’sqmnW) L21 April 3

19 I-V relation for n-MOS (ohmic reg)
ID non-physical ID,sat saturated VDS,sat VDS L21 April 3

20 Universal drain characteristic
ID VGS=VT+3V 9ID1 ohmic saturated, VDS>VGS-VT VGS=VT+2V 4ID1 VGS=VT+1V ID1 VDS L21 April 3

21 Characterizing the n-ch MOSFET
VD ID D G S B VT VGS L21 April 3

22 Low field ohmic characteristics
L21 April 3

23 MOSFET circuit parameters
L21 April 3

24 MOSFET circuit parameters (cont)
L21 April 3

25 Substrate bias effect on VT (body-effect)
L21 April 3

26 Body effect data Fig 9.9** L21 April 3

27 References *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 L21 April 3


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