1. Jie-Hong R. Jiang 江介宏 DEE/GIEE National Taiwan University
Applied Logic & Computation in System Design - An invitation to ALCom Lab
Jie-Hong R. Jiang
江介宏
DEE/GIEE
National Taiwan University
10/13/2006

2. About ALCom Lab Founded in August 2005
Caring about solving a good problem cleverly
We are cooking a pleasant research environment and a culture of creativity
Regular boardgame nights
Puzzle solving
Focus/study groups …
Aiming high and identifying a niche

3. New blood wanted!
We desperately eager for talented students joining us to claim challenging and exciting research projects
Yes, you are one of the talents!

4. Where are we heading?
Verification
Optimization
Foundations

5. Challenges Verification Optimization Foundations
60-80% design time is spent on verification
3-to-1 head count ratio between verification engineers and logic designers
Optimization
Stringent design constraints on power/timing/yield, etc.
Foundations
Design beyond silicon? New models of computation?

6. Equivalence verification
Algorithm ?
Architecture 1
(e.g. synchronous) 
Architecture 2
(e.g. asynchronous) ? =
register-transfer level ? = ?
gate level 1 =
gate level 2

7. Property verification
Identify invariants
Apply induction
Ex.
… + n +
n + n-1 + … + 1 ? x y
x-1 + 
Ex. ? x y
z = xy

8. Synthesis & optimization
Existing IP I O X

9. More info Contact me at Consult webpage at http://alcom.ee.ntu.edu.tw
Consult webpage at