1. EGR 2131 Unit 12 Synchronous Sequential Circuits
Read Brown & Vranesic, Sections 8.1 to 8.4, 8.9, and Sections A.10.10, A
Homework #12 and Lab #12 due next week.
Final Exam next week.
-Collect HW & Lab, and do Quiz.
-Handouts: Unit 12 practice sheet.

2. Synchronous Sequential Circuits (Finite State Machines)
Synchronous sequential circuits contain flip-flops that are all clocked by the same clock signal. They usually also contain combinational logic (gates).
Another name for this kind of circuit is finite state machine (FSM).
Registers, shift registers, and synchronous counters are simple examples of this type of circuit. Chapter 8 discusses analysis (Section 8.9) and design (Sections 8.1 to 8.7) of other examples. 2

3. Synchronous Sequential Circuits: General Form
W is the circuit’s non-clock input (if any).
Q is the value held in the circuit’s flip-flops.
Z is the circuit’s output. (In a simple case, Z = Q.)
W, Q, and Z may each be one bit or many bits. 3

4. Synchronous Sequential Circuits: Two Examples
An example that we’ll analyze below.
4-bit counter from Chapter 7. (Note that here we have no non-clock inputs, not much combinational logic on the input side, and no combinational logic on the output side.) 4

5. Review: Analysis of Combinational Circuits
Recall that with a combinational circuit such as the one shown, the inputs determine the outputs. So if you know the present input values, you can figure out the present output values. 5

6. Analysis of Synchronous Sequential Circuits
With a sequential circuit, knowing the present input values is not enough to let you figure out the present output values. You also need to know the values stored in each of the circuit’s flip-flops.
We call the collective values of the flip-flops the circuit’s state. 6

7. Analysis of Synchronous Sequential Circuits: Example
Suppose that in this circuit, you know that w = 0. Can you figure out the value of z?
No, not unless you also know the circuit’s state (i.e., the values stored in the two flip-flops).
This gets back to the idea of sequential circuits as having memory of their past, unlike combinational circuits. 7

8. Counters with Modified Count Sequences
A large class of FSMs consists of counters with modified count sequences, such as a 4-bit up counter that counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, … instead of counting all the way up to 15, as a “normal” 4-bit counter would do.
Some such circuits have crazy count sequences, such as 0, 6, 3, 5, 0… 8

9. Counters with Modified Count Sequences: Example
Problem 7.18 from the textbook: “This circuit looks like a counter. What is the sequence that the circuit counts in?”
Do as Practice Question 1. 9

10. State Diagram for a Counter-Like Circuit
A state diagram is a useful graphical device for showing the sequence of states through which a counter-like circuit progresses.
Example for a standard 3-bit counter:
Do Practice Question 2. 10

11. Analyzing More Complicated FSMs
FSMs with non-clock inputs and additional combinational logic are more difficult to analyze than the simple counter-like circuits discussed on the previous three slides.
We’ll use this previously pictured FSM to illustrate the process of analyzing such circuits. 11

12. State-Assigned Tables
Recall that when analyzing a combinational circuit we build a truth table, which lists the output values for every possible combination of input values.
When analyzing a sequential circuit we build a state-assigned table, which lists the output values and the next state for every possible combination of input values and the present state. 12

13. State-Assigned Table: Example
Here is a partial state-assigned table for the example circuit.
The first row says that if each flip-flop holds a 0, then:
Output z = 0 (right now).
If w = 0 (right now), both flip-flops will hold 0 after the next clock pulse.
But if w = 1 (right now), the lower flip-flop will hold 0 and the upper flip-flop will hold 1 after the next clock pulse.
Do as Practice Question 3. 13

14. State-Assigned Table: Example (Cont’d.)
For the table to be complete, it must list each combination of present state and non-clock input values.
Our example table covers every possible combination of values for y2, y1, and w.
Note, though, that our circuit, like many FSMs, also has a Reset input, which for simplicity is not shown in the state-assigned table. It’s understood that activating Reset will force the circuit to the 00 state. 14

15. “State Table” versus “State-Assigned Table”
A state table is similar to a state-assigned table, but a state table uses a single letter for each state, rather than showing the flip-flop values in each state.
When designing a circuit, you’ll typically make a state table first, and then a state-assigned table.
This terminology is not universal: some authors do not distinguish the two kinds of tables, using the term “state table” for either kind. 15

16. “State Table” versus “State-Assigned Table” for Our Example Circuit
For our example, suppose we call the 00 state A, and the 01 state B, and so on:
Clearly, the state table provides less detail than the state-assigned table.
Do as Practice Question 4. 16

17. State Diagram
A state diagram holds the same info as a state table but presents it in more graphical form.
Each state is represented by an oval-shaped node with the state letter and the corresponding output value written inside it.
Each possible state transition is represented by an arrow with a label that tells which input value results in this transition. 17

18. State Diagram: Example
This example of a state diagram does not match the state table from the previous slides.
Do Practice Question 5.
This arrow says that if we’re in State C and input w = 0, then on the next clock pulse we’ll transition to state A. 18

19. Sequential Circuit Analysis
Analysis of a sequential circuit starts with a logic diagram and ends with a state table or state diagram, and, possibly, a description in English of the circuit’s behavior.
On the previous 8 slides we’ve been analyzing a circuit whose logic diagram was given. Here’s a verbal description of this circuit’s behavior: “This circuit detects if three or more consecutive 1s occur on its input w.”
A circuit that detects the occurrence of a particular pattern on its input(s) is referred to as a sequence detector. 19

20. Analysis Versus Design
We’ve been discussing analysis of synchronous sequential circuits.
Recall that analysis starts with a logic diagram and ends with a state table or state diagram, and, possibly, a description in English of the circuit’s behavior.
The task of designing a sequential circuit reverses the order of the steps: we start with a verbal description of what the circuit is supposed to do, and our goal is a logic diagram of a circuit that behaves in that way.

21. “Classical” Design Procedure for Sequential Circuits
The following slides deal with the “classical” design procedure, which means the way it had to be done before the advent of computer-based tools such as VHDL combined with Quartus.
With these new tools, designers don’t need to do as much classical design, but you should still understand how to design a simple circuit the “old-fashioned way.”

22. Design Procedure: Basic Steps (See Textbook’s Section 8.1.6)
Obtain the specifications of the desired circuit.
Build a state diagram.
Build a state table.
Minimize the number of states.
Assign binary values to the states, resulting in a state-assigned table.
Choose the type of flip-flops to be used, and derive the simplified next-state logic expressions and simplified output logic expressions.
Implement and test the circuit.

23. Design Example Step 1: Obtain Specifications
Suppose we wish to design a circuit that meets the following specification:
The circuit has one input bit, w, and one output bit, z.
All changes in the circuit occur on the positive edge of a clock signal.
The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1. Otherwise, the value of z is equal to 0.

24. Design Example Step 1: Obtain Specifications (Cont’d.)
So the desired circuit is a sequence detector that detects if two or more consecutive 1s occur on the input w.
Sample sequence (incomplete) of input and output for the desired circuit:
Do as Practice Question 6.

25. Design Example Step 2: State Diagram
From the specifications we must create a state diagram. This may require a good bit of thought and trial-and-error.
Here is one possible start for our sequence detector:
Do as Practice Question 7.

26. Design Example Step 3: State Table
From the state diagram we create a state table. This step is usually easy.
Here is the beginning of a state table for our sequence detector:
Do as Practice Question 8.

27. Design Example Step 4: Minimize Number of States
For complex designs, your first attempt at a state diagram may contain more states than you really need. So it’s advantageous to reduce the number of states to the minimum required.
This may not be easy to do. The method is discussed in the textbook’s Section 8.6, “State Minimization”.
We’ll skip this step for our simple sequence detector.

28. Design Example Step 5: State-Assigned Table
Since our design has three states, we’ll need at least two flip-flops to keep track of the state that we’re in. (Two flip-flops are sufficient for designs with up to four states.) Calling these flip-flops y1 and y2, here’s a block-diagram of our circuit:

29. Design Example Step 5: State-Assigned Table (Cont’d.)
From the state table we create a state-assigned table. There will be more than one way to do this, and it’s not obvious which state assignment will result in the simplest final circuit.
For our sequence detector, let’s set y2y1 = 00 for State A, and y2y1 = 01 for State B, and y2y1 = 10 for State C. Then here is the beginning of the state-assigned table:
Do as Practice Question 9.

30. Design Example Step 6: Logic Expressions
Next we’ll use K-maps to design the two combinational circuits shown in the generic block diagram above. This means deriving expressions for Y1, Y2, and z.

31. Design Example Step 6: Logic Expressions (Cont’d.)
Here’s how to derive the expression for Y1 from the information in our state-assigned table.
Do as Practice Question 10.
𝑌 1 =𝑤 𝑦 𝑦 2

32. Design Example Step 7: Implement Circuit
The logic expressions from the previous step tell us what gates we need in the two combinational circuits shown above, so now we can draw a complete circuit diagram.

33. Moore Machines versus Mealy Machines
Recall our diagram of the general form of an FSM:
A Moore machine is an FSM in which Z depends only on Q, not on W (the pink line does not exist.)
A Mealy machine is an FSM in which Z depends on both Q and W (the pink line does exist.)
Our examples so far have all been Moore machines. 33