15. Example：
Precharge
Evaluation

16. (B) C2-MOS (Clocked CMOS) Logic
Version 1： 　　　　　　　　　　　Version 2：
CK=1：Active；CK=0：Disable
Mp , Mn Switching or isolating devices
Suitable for FF construct

20. Clock Skew Nat all clock arrive at the same time Two Problem：
-adds more overhead：
Tcyc = Td + Tsetup + Tclk-q + Tskew
-Get the wrong answer：
Tskew < Tclk-q + Thold
Low overhead =>Fast latches，low clock skew.

21. H-Tree(1)

22. Single clock Distribution - 21064
Thick metal layer for clock
M3 - 2μ thick
Large clock buffer
(entire vertical height of the chip)