1. CSc 352 An Introduction to make
Saumya Debray
Dept. of Computer Science
The University of Arizona, Tucson

2. Structuring large applications
So far, all of our programs have involved a single source file
obviously impractical for large(r) programs
even where practical, may not be good from a design perspective
If an application is broken up into multiple files, we need to manage the build process:
how do we (re)compile the various different files that make up the application?

3. Structuring large applications
When one file is edited, other files may need to be recompiled
changes to typedefs or macros in header files
changes to types of shared variables
Applications can contain a lot of files
E.g.: Linux kernel source code:  4,900 files
Recompiling all files whenever any file is changed can be very time-consuming.

4. Structuring large applications
Obvious idea: only recompile those files that need to be recompiled.

5. Structuring large applications
Obvious idea: only recompile those files that may be affected by a change.
affected
changed

6. Structuring large applications
“Smart recompilation” : issues
need to be able to express, keep track of dependencies between files
“dependency”  which files are (might be) affected by a change to a file?
need to make sure that all (and only) affected files are recompiled
doing this manually is tedious and error-prone
want an automated solution
make: a tool to automate recompilation of parts of a project based on a file of dependencies (“make file”)

7. Digression: compiling multi-file programs
gcc OPTS -c
file1.c
file1.o
gcc OPTS -c
file2.c
file2.o
gcc
executable …
gcc OPTS -c
fileN.c
fileN.o

8. Digression: compiling multi-file programs
gcc OPTS -c
file1.c
file1.o
gcc OPTS -c
file2.c
file2.o
gcc
executable …
gcc OPTS -c
fileN.c
fileN.o
source files
Only one of these files contains main()

9. Digression: compiling multi-file programs
gcc OPTS -c
file1.c
file1.o
gcc OPTS -c
file2.c
file2.o
gcc
executable …
gcc OPTS -c
fileN.c
fileN.o
object files
machine code, but not executable

10. Digression: compiling multi-file programs
gcc OPTS -c
file1.c
file1.o
gcc OPTS -c
file2.c
file2.o
gcc
executable …
gcc OPTS -c
fileN.c
fileN.o
linker invocation
combines various *.o files together

11. Digression: compiling multi-file programs
gcc OPTS -c
file1.c
file1.o
gcc OPTS -c
file2.c
file2.o
gcc
executable …
gcc OPTS -c
fileN.c
fileN.o
gcc -c
compile to a linkable object
don’t worry about main()

12. make files make files specify: dependencies between files
how to update dependent files

13. make files make files specify: dependencies between files
how to update dependent files
dependency
how to update the dependent file to satisfy this dependency

14. make files make files specify: dependencies between files
how to update dependent files
dependency
how to update the dependent file to satisfy this dependency

15. make files: structure
Structure of a make file: Macros (optional) target … : prerequisites … command . . .
target: (usually) the name of a file that is created by a program
prerequisite: a file used as input to create the target
\t (tab)
rule
\t (tab)
command: an action carried out by make to (re)construct target

16. make files: an elementary example
Dependency structure:
make file:
spellcheck.h
spellcheck: spellcheck.c spellcheck.h
gcc –Wall spellcheck.c
include
spellcheck.c
dependencies
compile
spellcheck
must be a tab!

17. Creating a makefile What are the targets? For each target foo:
figure out which files are created from other files and which need to be re-created when any of those files change.
For each target foo:
what are the files which, if changed, would require us to re-create foo?
These are the prerequisites for foo (let’s say bar1 ... barn)
What commands do we use to (re-)create foo?
say: cmd1 ... cmdm

18. Creating a makefile The resulting rule for foo is: or:
foo: bar1 bar barn
cmd1
cmd2
...
cmdm
tab
tab
tab
or:
foo: bar1 bar barn
cmd1 ; cmd2 ; ... cmdm
tab

19. make files: an elementary example
Dependency structure:
spellcheck.h
why is this not a dependency?
include
spellcheck.c
dependencies
compile
spellcheck

20. make files: example 2
file1.o : file1.c hdrfile1.h gcc -Wall -g -c file1.c file2.o : file2.c hdrfile1.h hdrfile2.h gcc -Wall -g -c file2.c execFile : file1.o file2.o gcc file1.o file2.o -o execFile

21. make files: Macros Makes make files easier to write, modify Example:
define: Name = replacement list
use: $(Name)
Example:
CC = gcc
OPTLEV = –O2 # optimization level
CFLAGS = –Wall –g –D DEBUG $(OPTLEV) – c
. . .
file1.o : file1.c hdrfile1.h
$(CC) $(CFLAGS) file1.c

22. Internal Macros These are macros that are predefined in make.
Examples:
CC = cc
CXX = g++
LD = ld
Execute “make –p” to get a complete list
Unix environment variables are inherited by make as predefined macros
execute “printenv” to get a complete list

23. Using make Invocation: make [ -f makeFileName ] [ target ]
default: make searches (in order) for:
makefile
Makefile
default: builds the first target in the make file

24. How make works When invoked, begins processing the appropriate target
For each target, considers the prerequisites it depends on:
target : file1 file2 …
checks (recursively) whether each of filei (1) exists and (2) is more recent than the files that filei depends on;
if not, executes the associated command(s) to update filei
checks whether target exists and is more recent that filei
if not, executes the commands associated with target

25. How make works Make file Dependence structure
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
filec
fileb
filee
filed
filef
fileg
cmdd

26. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
current?
filec
fileb
filee
filed
filef
fileg
cmdd
changed

27. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
current?
current?
current?
filec
fileb
filee
filed
filef
fileg
cmdd
changed

28. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
current?
filea
current?
current?
filec
fileb
current?
filee
filed
filef
fileg
cmdd
changed

29. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
current?
current?
current?
filec
fileb ok
current?
filee
filed
filef
fileg
cmdd
changed

30. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
current?
current?
current?
filec
fileb
update!
filee
filed
filef
fileg
cmdd
changed

31. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
current?
current?
update!
filec
fileb
filee
filed
filef
fileg
cmdd
changed

32. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
current?
update!
filec
fileb
filee
filed
filef
fileg
cmdd
changed

33. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
update!
filea
filec
fileb
filee
filed
filef
fileg
cmdd
changed

34. How make works Make file make execution
filea : fileb filec cmda fileb : filee filed cmdb filec : filed filef cmdc filed : filef fileg
filea
filec
fileb
filee
filed
filef
fileg
cmdd
changed

35. Phony Targets
A phony target is one that is not the name of a file, e.g.:
“make clean” will remove a.out and *.o files
clean:
rm –f *.o a.out
phony target

36. cleanup actions will be executed even if there is a file named “clean”
Phony Targets
This won’t work if we (accidentally) create a file named “clean”
Fix:
.PHONY: clean
clean:
rm *.o a.out
clean:
rm –f *.o a.out
cleanup actions will be executed even if there is a file named “clean”

37. Command execution
Commands to update a target are executed by invoking a new subshell for each command line
invoking commands like “cd” on one command line won’t affect other command lines
to have one command affect the next, put them on the same line, e.g.:
cd targetDir ; cmd
If a command returns an error (nonzero exit status), make abandons that rule
to ignore errors in a command, precede with ‘-’

38. Command execution The shell used is given by the macro SHELL
defaults to /bin/sh
[Ubuntu]: /bin/sh points to dash, a stripped-down version of bash
to use a different shell, define SHELL appropriately, e.g.:
SHELL = /bin/csh

39. Telling make how to process files
Suffix Rules:
Structure:
.suf1.suf2:
recipe
Example:
.c.o: …
Pattern Rules:
Structure:
%.suf2 : %.suf1
recipe
Example:
%.o : %.c …
To create a file foo.suf2 from foo.suf1, execute recipe
(suf1 comes before suf2: confusing)
Need a way to refer to a particular C file
“compile this file in this way…”

40. Telling make how to process files
Suffix Rules:
Structure:
.suf1.suf2:
recipe
Example:
.c.o: …
Pattern Rules:
Structure:
%.suf2 : %.suf1
recipe
Example:
%.o : %.c …
To create a file foo.suf2 from foo.suf1, execute recipe
(suf1 comes before suf2: confusing)
make has a list of known suffixes. These include .c and .o
To create your custom suffix rules for other suffixes, mention the suffixes to make, e.g.:
.SUFFIX: .foo .bar

41. Special Macros
These are macros defined internally for each dependency line:
full name of current target $*
basename of current target (i.e., target without its file extension)
$<
(inference rules) the single prerequisite that causes execution of the rule $?
list of all prerequisites newer than target
Example:
.dvi.ps:
dvips $< -o $*.ps
describes how to create a .ps file from a .dvi file.

42. Gnu Make String Functions
General syntax: $(funcName args or ${funcName args}
Most useful for us:
$(subst fromStr,toStr,txtStr)
replaces each occurrence of fromStr by toStr in txtStr
$(patsubst pattern,replacement,txtStr)
finds whitespace-separated words in txtStr that match pattern and replaces them with replacement. “%” can be used as a wildcard.
$(var:suffix=replacement)
replaces suffix at the end of filenames in var by replacement
$(wildcard pattern)
replaced by a space-separated list of file names that match pattern

43. Examples Goal: convert PDF files to HTML using pdftohtml Suffix rules:
.pdf.html:
pdftohtml $<
subst:
PDFS = file1.pdf file2.pdf file3.pdf
HTMLS = $(subst .pdf,.html,$(PDFS))
all : $(HTMLS)
pdftohtml $<
patsubst:
HTMLS = $(patsubst %.pdf,%.html,$(PDFS))
Suffix replacement:
HTMLS = $(PDFS:pdf=html)

44. Examples getting all the C files in the directory:
CFILES = $(wildcard *.c)

45. Topics not covered
make has a lot of functionality we won’t get to cover, e.g.:
implicit rules
implicit variables
conditional parts of make files
recursively running make in subdirectories
See online make tutorials for more information